# US 12,218,020 B2 · Semiconductor packages

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- Number: US 12,218,020 B2
- Document ID: US12218020B2
- Status: Granted
- Kind: B2
- Application number: 17/695,864
- Filed: 2022-03-16
- Published: 2022-06-30
- Granted: 2025-02-04
- Earliest claimed: 2018-11-29
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Jiun-Yi Wu; Chen-Hua Yu; Chung-Shi Liu; Yu-Min Liang
- Web page: https://patentgrep.com/patent/US12218020B2

## CPC

- H10W 70/611: {for connecting multiple chips together}
- H10W 74/121: {by multiple encapsulations, e.g. by a thin protective coating and a thick encapsulation}
- H10P 72/74: {using temporarily an auxiliary support}
- H10W 70/618: {the bridge chips being embedded in the package substrates, interposers or redistribution layers}
- H10W 70/635: {Through-vias}
- H10W 70/685: comprising multiple insulating layers
- H10W 70/695: Organic materials
- H10W 72/20: Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
- H10W 74/01: Manufacture or treatment
- H10W 74/012: {of encapsulations on active surfaces of flip-chip devices, e.g. forming underfills}
- H10W 74/019: {using temporary auxiliary substrates (H10W74/017 takes precedence)}
- H10W 74/117: {the substrate having spherical bumps for external connection}
- H10W 74/127: {characterised by arrangements for sealing or adhesion}
- H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills
- H10W 90/00: Package configurations
- H10W 90/401: {characterised by multiple insulating or insulated package substrates, interposers or RDLs}
- H05K 1/185: associated with components encapsulated in the insulating substrate of the PCBs; associated with components incorporated in internal layers of multilayer circuit boards
- H05K 3/4602: {characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated}
- H05K 3/4644: {by building the multilayer layer by layer, i.e. build-up multilayer circuits (making via holes in the insulating layers H05K3/0011; special circuit boards as base or core whereon the multilayer is built H05K3/4602)}
- H05K 2201/10159: Memory
- H05K 2201/10166: Transistor
- H05K 2203/163: Monitoring a manufacturing process
- H10P 72/7424: {used as a support during the manufacture of self-supporting substrates}
- H10P 72/743: {used as a support during manufacture of interconnect decals or build up layers}
- H10P 72/7436: {used to support a device or a wafer when forming electrical connections thereto}
- H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40)
- H10W 72/07254: {changes in dispositions}
- H10W 72/241: {Dispositions, e.g. layouts}
- H10W 72/247: {Dispositions of multiple bumps}
- H10W 74/142: {the encapsulations exposing the passive side of the semiconductor body}
- H10W 90/20: Configurations of stacked chips
- H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts}
- H10W 90/722: {between stacked chips}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H05K: PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS

## Abstract

A semiconductor package includes a circuit structure, a first redistribution layer, a second redistribution layer, a first encapsulant, a bus die and a plurality of through vias. The first redistribution layer is disposed over the circuit structure. The second redistribution layer is disposed over the first redistribution layer. The first encapsulant is disposed between the first redistribution layer and the second redistribution layer. The through vias surround the bus die. The first encapsulant is extended along an entire sidewall of the bus die, and a first surface of the bus die is substantially coplanar with top surfaces of the first encapsulant and the plurality of through vias.

## Claims

### Claim 1

A semiconductor package, comprising:
a circuit structure;
a first redistribution layer over the circuit structure;
a second redistribution layer over the first redistribution layer;
a first encapsulant, disposed between the first redistribution layer and the second redistribution layer, wherein the first encapsulant comprises a molding compound; and
a bus die and a plurality of through vias surrounding the bus die, wherein the bus die comprises a substrate and a plurality of conductive patterns on the substrate, an entire sidewall of each of the conductive patterns of the bus die is continuous without a turning point, the first encapsulant is a single layer and extended along an entire sidewall of the substrate, the entire sidewall of each of the conductive patterns and an entire sidewall of each of the through vias, and top surfaces of the conductive patterns of the bus die are coplanar with top surfaces of the first encapsulant and the plurality of through vias.

### Claim 2 (depends on 1)

The semiconductor package according to claim 1, wherein the circuit structure comprises a core layer, a first build-up layer on a first surface of the core layer, and a second build-up layer on a second surface of the core layer opposite to the first surface.

### Claim 3 (depends on 1)

The semiconductor package according to claim 1, further comprising a plurality of semiconductor devices and a second encapsulant encapsulating the semiconductor devices over the second redistribution layer.

### Claim 4 (depends on 1)

The semiconductor package according to claim 1, wherein sidewalls of the first redistribution layer, the second redistribution layer and the first encapsulant are substantially flush.

### Claim 5 (depends on 1)

The semiconductor package according to claim 1, wherein a bottom surface of the bus die is substantially coplanar with bottom surfaces of the first encapsulant and the plurality of through vias.

### Claim 6 (depends on 1)

The semiconductor package according to claim 1, wherein the bus die comprises an adhesive layer adhered to the first redistribution layer, and a bottom surface of the adhesive layer is coplanar with bottom surfaces of the first encapsulant and the plurality of through vias.

### Claim 7 (depends on 1)

The semiconductor package according to claim 1, wherein the entire sidewall of each of the through vias is continuous without a turning point.

### Claim 8

A semiconductor package, comprising:
a first redistribution layer comprising a first insulating layer;
a connector and a first die encapsulated by a first encapsulant over the first redistribution layer;
a second redistribution layer over the first encapsulant and comprising a second insulating layer and a plurality of first conductive patterns in the second insulating layer; and
a second die over the second redistribution layer, electrically connected to the first die, wherein the first encapsulant comprises a molding compound, a material of each of the first insulating layer and the second insulating layer is not the molding compound, top surfaces of a plurality of second conductive patterns of the first die are coplanar with top surfaces of the first encapsulant and the connector, and sidewalls of the first redistribution layer, the second redistribution layer and the first encapsulant are substantially flush.

### Claim 9 (depends on 8)

The semiconductor package according to claim 8, wherein the first encapsulant is disposed between the connector and the first die.

### Claim 10 (depends on 8)

The semiconductor package according to claim 8, further comprising a second encapsulant encapsulating the second die, wherein a sidewall of the second encapsulant is substantially flush with the sidewalls of the first redistribution layer, the second redistribution layer and the first encapsulant.

### Claim 11 (depends on 8)

The semiconductor package according to claim 8, further comprising a circuit structure, wherein the first redistribution layer is disposed over the circuit structure, the circuit structure includes a core layer, a first build-up layer on a first surface of the core layer, and a second build-up layer on a second surface of the core layer opposite to the first surface.

### Claim 12 (depends on 8)

The semiconductor package according to claim 8, wherein a bottom surface of the first die is coplanar with bottom surfaces of the connector and the first encapsulant.

### Claim 13 (depends on 8)

The semiconductor package according to claim 8, wherein the first encapsulant is in direct contact with the first insulating layer and the second insulating layer.

### Claim 14

A semiconductor package, comprising:
a first redistribution layer comprising a plurality of first insulating layers and a plurality of first conductive patterns in the first insulating layers;
a second redistribution layer over the first redistribution layer, comprising a plurality of second insulating layers and a plurality of second conductive patterns in the second insulating layers; and
a first encapsulant, a bus die and a plurality of through vias, disposed between the first redistribution layer and the second redistribution layer, wherein the first encapsulant comprises a molding compound, top surfaces of a plurality of third conductive patterns of the bus die are coplanar with top surfaces of the first encapsulant and the plurality of through vias, and sidewalls of the first insulating layers, the second insulating layers and the first encapsulant are substantially flush, and the second conductive patterns are bonded to conductive connectors of a die through solder regions.

### Claim 15 (depends on 14)

The semiconductor package according to claim 14, wherein the first encapsulant is in physical contact with sidewalls of the plurality of third conductive patterns.

### Claim 16 (depends on 14)

The semiconductor package according to claim 14, wherein the bus die comprises an adhesive layer, and a surface of the adhesive layer is substantially coplanar with bottom surfaces of the plurality of through vias.

### Claim 17 (depends on 16)

The semiconductor package according to claim 16, wherein the adhesive layer is in physical contact with first conductive patterns in the first redistribution layer.

### Claim 18 (depends on 14)

The semiconductor package according to claim 14, wherein the top surfaces of the third conductive patterns of the bus die are further coplanar with a bottom surface of a bottommost one of the second insulating layers of the second redistribution layer.

### Claim 19 (depends on 18)

The semiconductor package according to claim 18, wherein a material of the second insulating layers comprises polyimide, polybenzoxazole (PBO), benzocyclobutene (BCB), phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), silicon nitride, silicon oxide or a combination thereof.

### Claim 20 (depends on 14)

The semiconductor package according to claim 14, wherein the second conductive patterns comprise a plurality of conductive vias and a plurality of conductive pads directly bonded to the conductive connectors of the die through the solder regions.