# US 12,218,018 B2 · Semiconductor encapsulant strength enhancer

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- Number: US 12,218,018 B2
- Document ID: US12218018B2
- Status: Granted
- Kind: B2
- Application number: 17/726,045
- Filed: 2022-04-21
- Published: 2023-10-26
- Granted: 2025-02-04
- Earliest claimed: 2022-04-21
- Assignees: Infineon Technologies AG
- Applicants: Infineon Technologies AG
- Inventors: Georg Troska; Hans Hartung
- Web page: https://patentgrep.com/patent/US12218018B2

## CPC

- H10W 76/47: Solid or gel fillings
- H10W 76/48: Fillings including materials for absorbing or reacting with moisture or other undesired substances
- H10W 42/121: {protecting against mechanical damage (H10W76/00, H10W74/00 take precedence)}
- H10W 74/01: Manufacture or treatment
- H10W 74/111: {the semiconductor body being completely enclosed}
- H10W 74/114: {by a substrate and the encapsulations}
- H10W 74/127: {characterised by arrangements for sealing or adhesion}
- H10W 74/476: {Organic materials comprising silicon}
- H10W 76/15: Containers comprising an insulating or insulated base
- H10W 76/40: Fillings or auxiliary members in containers, e.g. centering rings (fillings or auxiliary members for thermal protection or control in containers or encapsulations H10W40/70)
- H10W 40/255: {having a laminate or multilayered structure, e.g. direct bond copper [DBC] ceramic substrates}
- H10W 74/43: comprising oxides, nitrides or carbides, e.g. ceramics or glasses
- H10W 74/473: {containing a filler}
- H10W 90/00: Package configurations
- H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor module includes a power electronics carrier including a structured metallization layer disposed on an electrically insulating substrate, a power semiconductor die mounted on the power electronics carrier, a housing that surrounds an interior volume over the power electronics carrier, a reinforcing structure contained within the interior volume and including a textured surface that is accessible by fluid, a volume of curable encapsulant disposed within the interior volume and encapsulating the power semiconductor die, wherein the reinforcing structure is embedded within the volume of curable encapsulant such that the textured surface adheres to the encapsulant, and wherein the reinforcing structure has a tensile strength that is greater than a tensile strength of the curable encapsulant.

## Claims

### Claim 1

A semiconductor module, comprising:
a power electronics carrier comprising a structured metallization layer disposed on an electrically insulating substrate;
a power semiconductor die mounted on the power electronics carrier;
a housing comprising sidewalls that surround an interior volume over the power electronics carrier;
a reinforcing structure contained within the interior volume and comprising a textured surface that is accessible by fluid;
a volume of curable encapsulant disposed within the interior volume and encapsulating the power semiconductor die,
wherein the reinforcing structure is embedded within the volume of curable encapsulant such that the textured surface adheres to the encapsulant,
wherein the reinforcing structure has a tensile strength that is greater than a tensile strength of the curable encapsulant, and
wherein the reinforcing structure comprises a material with a coefficient of thermal expansion that is equal to or less than a coefficient of thermal expansion of the encapsulant.

### Claim 2 (depends on 1)

The semiconductor module of claim 1, wherein the reinforcing structure comprises a network of cells, and wherein the cells at least partially absorb the encapsulant.

### Claim 3 (depends on 2)

The semiconductor module of claim 2, wherein the cells form a three-dimensional grid.

### Claim 4 (depends on 3)

The semiconductor module of claim 3, wherein the reinforcing structure is an foam or sponge.

### Claim 5 (depends on 3)

The semiconductor module of claim 3, wherein the reinforcing structure comprises any one or more of: duroplastics, elastomers, and silicone.

### Claim 6 (depends on 1)

The semiconductor module of claim 1, wherein the reinforcing structure comprises any one or more of: a woven fabric, and a plurality of disconnected filler elements.

### Claim 7 (depends on 1)

The semiconductor module of claim 1, wherein the curable encapsulant and the reinforcing structure are each formed from dielectric materials.

### Claim 8 (depends on 7)

The semiconductor module of claim 7, wherein the curable encapsulant is a silicone-based potting compound.

### Claim 9 (depends on 1)

The semiconductor module of claim 1, wherein the reinforcing structure has a lower coefficient of thermal expansion than the encapsulant.

### Claim 10

A semiconductor device, comprising:
an encapsulant body of electrically insulating encapsulant material;
a semiconductor die encapsulated within the encapsulant body; and
a reinforcing structure contained within the encapsulant body and arranged between the semiconductor die and an outer surface of the encapsulant body,
wherein the reinforcing structure comprises a textured surface area that is accessible by fluid,
wherein the reinforcing structure is embedded within the encapsulant body such that the textured surface adheres to the encapsulant material, and
wherein the reinforcing structure has a tensile strength that is greater than a tensile strength of the curable encapsulant, and
wherein the reinforcing structure comprises a material with a coefficient of thermal expansion that is equal to or less than a coefficient of thermal expansion of the encapsulant.

### Claim 11 (depends on 10)

The semiconductor device of claim 10, wherein the reinforcing structure comprises a network of cells, wherein the cells at least partially absorb the encapsulant, and wherein the cells form a three-dimensional grid.

### Claim 12

A method of producing a semiconductor module, the method comprising:
providing a power electronics carrier comprising a structured metallization layer disposed on an electrically insulating substrate;
mounting a power semiconductor die on the power electronics carrier;
providing a housing comprising sidewalls that surround an interior volume over the power electronics carrier;
providing a reinforcing structure within the interior volume that comprises a textured surface area; and
providing a curable encapsulant disposed within the interior volume that encapsulates the power semiconductor die,
wherein the reinforcing structure is embedded within volume of curable encapsulant such that the textured surface area adheres to the encapsulant, and
wherein the reinforcing structure has a tensile strength that is greater than a tensile strength of the curable encapsulant,
wherein the reinforcing structure comprises a material with a coefficient of thermal expansion that is equal to or less than a coefficient of thermal expansion of the encapsulant.

### Claim 13 (depends on 12)

The method of claim 12, wherein the reinforcing structure is provided within the interior volume before providing the curable encapsulant, and wherein providing the curable encapsulant comprises:
flowing the curable encapsulant in a liquified state into the interior volume so as to cover the power semiconductor die and interact with the textured surface area; and
hardening the encapsulant such that the reinforcing structure is inseparable from the curable encapsulant.

### Claim 14 (depends on 13)

The method of claim 13 wherein the reinforcing structure comprises a network of cells, and wherein the cells are dimensioned to permit the liquefied state encapsulant to flow into them during the flowing of the curable encapsulant.

### Claim 15 (depends on 14)

The method of claim 14, wherein the cells form a three-dimensional grid.

### Claim 16 (depends on 13)

The method of claim 13, wherein the reinforcing structure distributes the curable encapsulant into a plurality of distributed regions that permit compression and expansion of the encapsulant during thermal cycling.

### Claim 17 (depends on 16)

The method of claim 16, wherein the power semiconductor die has a maximum operating temperature of at least 75° C.

### Claim 18 (depends on 12)

The method of claim 12, wherein the curable encapsulant comprises a dielectric gel.

### Claim 19 (depends on 18)

The semiconductor module of claim 18, wherein the dielectric gel is a silicone-based potting compound.