# US 12,218,016 B2 · Semiconductor structure

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 12,218,016 B2
- Document ID: US12218016B2
- Status: Granted
- Kind: B2
- Application number: 17/479,154
- Filed: 2021-09-20
- Published: 2022-03-10
- Granted: 2025-02-04
- Earliest claimed: 2020-09-04
- Assignees: Changxin Memory Technologies, Inc.
- Applicants: Changxin Memory Technologies, Inc.
- Inventors: Chen Huang; Meng-Feng Tsai; Yuejiao Shu
- Web page: https://patentgrep.com/patent/US12218016B2

## CPC

- H10P 74/273: {Interconnections for measuring or testing, e.g. probe pads}
- H10P 74/277: {Circuits for electrically characterising or monitoring manufacturing processes, e.g. circuits in tested chips or circuits in testing wafers}
- H10P 74/00: Testing or measuring during manufacture or treatment of wafers, substrates or devices
- H10W 20/43: Layouts of interconnections
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor structure is provided with a test region. In test region, the semiconductor structure includes a semiconductor substrate, a plurality of bit line contact structures arranged on semiconductor substrate and a plurality of wire groups. The semiconductor structure is provided with a plurality of separate active regions extending along a first direction. In first direction, each active region is electrically connected to two bit line contact structures. The plurality of wire groups are arranged along a second direction. Each wire group includes a plurality of wires extending along a third direction. In third direction, each of two bit line contact structures for each active region is connected to respective one of two bit line contact structures for active region adjacent to said each active region by a respective one of wires, so that two wire groups of the wire groups cooperate with each other to form a conductive path.

## Claims

### Claim 1

A semiconductor structure, wherein the semiconductor structure is provided with a test region, and in the test region, the semiconductor structure comprises:
a semiconductor substrate provided with a plurality of separate active regions extending along a first direction;
a plurality of bit line contact structures arranged on the semiconductor substrate, wherein in the first direction, each active region is electrically connected to two bit line contact structures; and
a plurality of wire groups arranged along a second direction, wherein each wire group comprises a plurality of wires extending along a third direction, and in the third direction, each of the two bit line contact structures for each active region is connected to a respective one of the two bit line contact structures for the active region adjacent to said each active region by a respective one of the wires, so that two wire groups of the wire groups cooperate with each other to form a conductive path;
wherein the wires in different wire groups re misaligned with each other in a fourth direction;
wherein the plurality of wires in each group are formed by cutting an entire wire in the fourth direction according to a set distance, and an end of each wire is inclined in the fourth direction;
wherein an angle between the fourth direction and the second direction is a preset value, and the preset value is set according to a pattern of the bit line contact structures to avoid the bit line contact structures from being destroyed during the cutting; and
wherein the preset value ranges from 30 degrees to 50 degrees.

### Claim 2 (depends on 1)

The semiconductor structure of claim 1, wherein the wires in a same wire group or the wires in different wire groups have a same length.

### Claim 3 (depends on 1)

The semiconductor structure of claim 1, wherein the wires in a same wire group are equally spaced apart from each other.

### Claim 4 (depends on 1)

The semiconductor structure of claim 1, wherein an angle between the second direction and the third direction is 90 degrees.

### Claim 5 (depends on 1)

The semiconductor structure of claim 1, wherein the bit line contact structures form a plurality of bit line contact structure groups arranged along the second direction.

### Claim 6 (depends on 5)

The semiconductor structure of claim 5, wherein the bit line contact structures in each bit line contact structure group are arranged along the third direction.

### Claim 7 (depends on 1)

The semiconductor structure of claim 1, wherein the semiconductor structure further comprises an array region, and a length of the active regions located in the test region is greater than a length of the active regions located in the array region.

### Claim 8 (depends on 7)

The semiconductor structure of claim 7, wherein the length of the active regions located in the test region is twice the length of the active regions located in the array region.

### Claim 9 (depends on 1)

The semiconductor structure of claim 1, wherein the first direction is a direction that forms an acute angle with a horizontal direction.

### Claim 10 (depends on 1)

The semiconductor structure of claim 1, wherein the second direction is a horizontal direction.

### Claim 11 (depends on 1)

The semiconductor structure of claim 1, wherein each bit line contact structure is a conductive structure.

### Claim 12 (depends on 1)

The semiconductor structure of claim 1, wherein in the first direction, a set distance is formed between the two bit line contact structures.

### Claim 13 (depends on 1)

The semiconductor structure of claim 1, wherein an angle between the second direction and the third direction is an acute angle.