# US 12,218,009 B2 · Semiconductor package and methods of forming the same

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- Number: US 12,218,009 B2
- Document ID: US12218009B2
- Status: Granted
- Kind: B2
- Application number: 18/363,458
- Filed: 2023-08-01
- Published: 2023-11-23
- Granted: 2025-02-04
- Earliest claimed: 2018-10-31
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Meng-Che Tu; Wei-Chih Chen; Sih-Hao Liao; Yu-Hsiang Hu; Hung-Jui Kuo; Chen-Hua Yu
- Web page: https://patentgrep.com/patent/US12218009B2

## CPC

- H10D 84/01: Manufacture or treatment
- H10W 74/019: {using temporary auxiliary substrates (H10W74/017 takes precedence)}
- H10D 86/01: Manufacture or treatment
- H10D 87/00: Integrated devices comprising both bulk components and either SOI or SOS components on the same substrate
- H10P 72/74: {using temporarily an auxiliary support}
- H10W 70/09: extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs
- H10W 72/20: Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
- H10W 72/90: Bond pads, in general
- H10W 74/014: {using batch processing}
- H10W 74/016: {using moulds}
- H10W 74/111: {the semiconductor body being completely enclosed}
- H10P 72/7424: {used as a support during the manufacture of self-supporting substrates}
- H10W 70/099: {Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers}
- H10W 70/65: Shapes or dispositions of interconnections
- H10W 70/6528: {of the portions that connect to chips, wafers or package parts}
- H10W 72/0198: {batch processes}
- H10W 72/073: {of die-attach connectors}
- H10W 72/241: {Dispositions, e.g. layouts}
- H10W 72/874: {On different surfaces}
- H10W 72/9413: {on encapsulations}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A method of forming a semiconductor device includes forming a first dielectric layer over a front side of a wafer, the wafer having a plurality of dies at the front side of the wafer, the first dielectric layer having a first shrinkage ratio smaller than a first pre-determined threshold; curing the first dielectric layer at a first temperature, where after curing the first dielectric layer, a first distance between a highest point of an upper surface of the first dielectric layer and a lowest point of the upper surface of the first dielectric layer is smaller than a second pre-determined threshold; thinning the wafer from a backside of the wafer; and performing a dicing process to separate the plurality of dies into individual dies.

## Claims

### Claim 1

A method of forming a semiconductor device, the method comprising:
forming a first dielectric material over a passivation layer of a die and over a die connector of the die, the die connector extending through the passivation layer;
curing the first dielectric material, wherein after curing the first dielectric material, the cured first dielectric material comprises:
a first portion over and contacting the die connector; and
a second portion laterally spaced apart from the die connector, wherein the first portion extends further from the passivation layer than the second portion;
forming a second dielectric material over the cured first dielectric material; and
curing the second dielectric material, wherein after curing the second dielectric material, the cured second dielectric material comprises:
a third portion over and contacting the first portion of the cured first dielectric material; and
a fourth portion over the second portion of the cured first dielectric material, wherein the third portion is thinner than the fourth portion.

### Claim 2 (depends on 1)

The method of claim 1, wherein a first shrinkage ratio of the first dielectric material is larger than a second shrinkage ratio of the second dielectric material.

### Claim 3 (depends on 2)

The method of claim 2, wherein the first shrinkage ratio is between about 50% and about 80%, and the second shrinkage ratio is less than about 5%.

### Claim 4 (depends on 1)

The method of claim 1, wherein a first vertical distance between a highest point of an upper surface of the cured first dielectric material and a lowest point of the upper surface of the cured first dielectric material has a first value, wherein a second vertical distance between a highest point of an upper surface of the cured second dielectric material and a lowest point of the upper surface of the cured second dielectric material has a second value, wherein the first value is larger than the second value.

### Claim 5 (depends on 1)

The method of claim 1, wherein an upper surface of the cured second dielectric material distal from the passivation layer is substantially flat.

### Claim 6 (depends on 1)

The method of claim 1, further comprising:
attaching a backside of the die to a carrier;
forming a molding material over the carrier and around the die; and
forming a redistribution structure over the molding material, the redistribution structure being electrically coupled to the die.

### Claim 7 (depends on 6)

The method of claim 6, further comprising, after forming the molding material and before forming the redistribution structure:
performing a planarization process to remove at least the first portion of the cured first dielectric material and the third portion of the cured second dielectric material, wherein after the planarization process, the die connector is exposed by the cured first dielectric material and the cured second dielectric material.

### Claim 8 (depends on 7)

The method of claim 7, wherein after the planarization process, the die connector, the cured first dielectric material, and the cured second dielectric material have a coplanar upper surface.

### Claim 9 (depends on 7)

The method of claim 7, wherein after the planarization process, a remaining portion of the cured first dielectric material contacts the die connector, and a remaining portion of the cured second dielectric material is separated from the die connector by the remaining portion of the cured first dielectric material.

### Claim 10 (depends on 7)

The method of claim 7, wherein the planarization process removes the cured second dielectric material from an upper surface of the cured first dielectric material, wherein after the planarization process, the die connector and remaining portions of the cured first dielectric material have a coplanar upper surface.

### Claim 11

A method of forming a semiconductor device, the method comprising:
depositing a first dielectric material over a passivation layer of a die and over a die connector of the die, the die connector extending through the passivation layer, wherein the first dielectric material has a first shrinkage ratio;
curing the first dielectric material;
after curing the first dielectric material, depositing a second dielectric material over the first dielectric material, wherein the second dielectric material has a second shrinkage ratio different from the first shrinkage ratio; and
curing the second dielectric material.

### Claim 12 (depends on 11)

The method of claim 11, wherein the second shrinkage ratio is smaller than the first shrinkage ratio.

### Claim 13 (depends on 11)

The method of claim 11, wherein after curing the first dielectric material, the first dielectric material has a curved upper surface distal to the passivation layer, wherein the curved upper surface comprises:
a first region over the die connector; and
a second region laterally adjacent to the die connector, wherein the first region extends further from the passivation layer than the second region.

### Claim 14 (depends on 13)

The method of claim 13, further comprising, after curing the second dielectric material:
forming a molding material around and over the die;
performing a planarization process to remove at least portions of the first dielectric material, portions of the second dielectric material, and portions of the molding material, and to expose the die connector; and
after performing the planarization process, forming a redistribution structure over the molding material and electrically coupled to the die connector.

### Claim 15 (depends on 14)

The method of claim 14, wherein after the planarization process, the die connector, the second dielectric material, and the first dielectric material have a coplanar upper surface.

### Claim 16 (depends on 11)

The method of claim 11, wherein the first shrinkage ratio is between about 50% and about 80%, and the second shrinkage ratio is less than about 5%.

### Claim 17

A method of forming a semiconductor device, the method comprising:
forming a first dielectric material over a front side of a wafer, the wafer having a plurality of dies at the front side of the wafer, the first dielectric material having a first shrinkage ratio smaller than a pre-determined shrinkage ratio;
curing the first dielectric material, wherein after curing the first dielectric material, a first vertical distance between a highest point of an upper surface of the first dielectric material and a lowest point of the upper surface of the first dielectric material is smaller than a pre-determined distance value; and
dicing the wafer to separate the plurality of dies into individual dies.

### Claim 18 (depends on 17)

The method of claim 17, further comprising:
attaching a die of the individual dies to a carrier;
forming a molding material on the carrier around the die; and
forming a redistribution structure over the molding material and electrically coupled to the die.

### Claim 19 (depends on 17)

The method of claim 17, wherein the pre-determined shrinkage ratio is 1%, and the pre-determined distance value is 4 μm.

### Claim 20 (depends on 17)

The method of claim 17, further comprising, before forming the first dielectric material:
forming a second dielectric material over the front side of the wafer, the second dielectric material having a second shrinkage ratio larger than the pre-determined shrinkage ratio; and
curing the second dielectric material, wherein after curing the second dielectric material, a second vertical distance between a highest point of an upper surface of the second dielectric material and a lowest point of the upper surface of the second dielectric material is larger than the pre-determined distance value.