# US 12,218,006 B2 · System, device and methods of manufacture

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- Number: US 12,218,006 B2
- Document ID: US12218006B2
- Status: Granted
- Kind: B2
- Application number: 18/503,453
- Filed: 2023-11-07
- Published: 2024-02-29
- Granted: 2025-02-04
- Earliest claimed: 2019-12-27
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Chen-Hua Yu; Wei Ling Chang; Chuei-Tang Wang; Tin-Hao Kuo; Che-Wei Hsu
- Web page: https://patentgrep.com/patent/US12218006B2

## CPC

- H10W 20/0698: {Local interconnections}
- H10W 70/05: of insulating or insulated package substrates, or of interposers, or of redistribution layers (manufacture or treatment of leadframes H10W70/04)
- H10D 84/01: Manufacture or treatment
- H10D 86/01: Manufacture or treatment
- H10D 87/00: Integrated devices comprising both bulk components and either SOI or SOS components on the same substrate
- H10W 20/023: {the interconnections being through-semiconductor vias}
- H10W 20/0245: {comprising use of blind vias during the manufacture}
- H10W 20/2134: {TSVs extending from the semiconductor wafer into back-end-of-line layers}
- H10W 20/40: Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
- H10W 20/43: Layouts of interconnections
- H10W 20/481: {on the rear surfaces of the wafers or substrates}
- H10W 70/611: {for connecting multiple chips together}
- H10W 70/635: {Through-vias}
- H10W 70/685: comprising multiple insulating layers
- H10W 72/019: {of bond pads}
- H10W 90/00: Package configurations
- H10B 10/18: {Peripheral circuit regions}
- H10D 84/00: Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D 86/201: {the substrates comprising an insulating layer on a semiconductor body, e.g. SOI (H10D86/40 take precedence)}
- H10W 40/60: Securing means for detachable heating or cooling arrangements, e.g. clamps
- H10W 40/611: {Bolts or screws}
- H10W 70/65: Shapes or dispositions of interconnections
- H10W 70/655: Fan-out layouts
- H10W 72/072: {of bump connectors}
- H10W 72/073: {of die-attach connectors}
- H10W 72/29: Bond pads specially adapted therefor
- H10W 72/877: {Bump connectors and die-attach connectors}
- H10W 72/944: {Dispositions of multiple bond pads}
- H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills
- H10W 90/722: {between stacked chips}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

Systems, devices and methods of manufacturing a system on silicon wafer (SoSW) device and package are described herein. A plurality of functional dies is formed in a silicon wafer. Different sets of masks are used to form different types of the functional dies in the silicon wafer. A first redistribution structure is formed over the silicon wafer and provides local interconnects between adjacent dies of the same type and/or of different types. A second redistribution structure may be formed over the first redistribution layer and provides semi-global and/or global interconnects between non-adjacent dies of the same type and/or of different types. An optional backside redistribution structure may be formed over a second side of the silicon wafer opposite the first redistribution layer. The optional backside redistribution structure may provide backside interconnects between functional dies of different types.

## Claims

### Claim 1

A method comprising:
forming a plurality of semiconductor dies at least partially within a semiconductor substrate;
forming a first local interconnect adjacent to a first side of the semiconductor substrate, wherein the first local interconnect electrically couples a first semiconductor die of the plurality of semiconductor dies to a second semiconductor die of the plurality of semiconductor dies, the first local interconnect passing across a scribe region disposed between the first semiconductor die and the second semiconductor die; and
forming an integrated fan-out structure adjacent to a second side of the semiconductor substrate opposite the first side, wherein the integrated fan-out structure electrically couples a third semiconductor die of the plurality of semiconductor dies to the first semiconductor die of the plurality of semiconductor dies.

### Claim 2 (depends on 1)

The method of claim 1, further comprising forming an intermediate device, wherein the first local interconnect electrically couples the intermediate device to the first semiconductor die and to the second semiconductor die.

### Claim 3 (depends on 1)

The method of claim 1, further comprising forming through-substrate vias through the semiconductor substrate, wherein the through-substrate vias electrically couple the integrated fan-out structure to the first local interconnect.

### Claim 4 (depends on 1)

The method of claim 1, further comprising forming a global interconnect structure over the first local interconnect, wherein the global interconnect structure electrically couples the first semiconductor die to the third semiconductor die, the second semiconductor die being in between the first semiconductor die and the third semiconductor die.

### Claim 5 (depends on 4)

The method of claim 4, further comprising attaching a power module to the global interconnect structure opposite the first local interconnect.

### Claim 6 (depends on 4)

The method of claim 4, further comprising attaching a receptor for high-speed serial digital interface cables to the global interconnect structure opposite the first local interconnect.

### Claim 7 (depends on 1)

The method of claim 1, wherein the first semiconductor die comprises a first function, the second semiconductor die comprises a second function, and the third semiconductor die comprises a third function, wherein the first function, the second function, and the third function are all different from each other.

### Claim 8 (depends on 7)

The method of claim 7, wherein the first semiconductor die is a digital signal processing core, the second semiconductor die is a central processing unit, and the third semiconductor die is a graphics processing unit.

### Claim 9

A method comprising:
forming a first die at least partially within a semiconductor substrate;
forming a second die at least partially within the semiconductor substrate;
forming a third die at least partially within the semiconductor substrate, the second die being between the first die and the third die;
forming a first set of metallization layers in direct physical contact with the first die and the second die, wherein the first die and the second die are electrically connected through the first set of metallization layers;
forming a second set of metallization layers on the first set of metallization layers opposite the first die and the second die, wherein the second set of metallization layers and the first set of metallization layers electrically connect the third die and the first die, wherein the first set of metallization layers is between the semiconductor substrate and the second set of metallization layers; and
forming a backside redistribution structure on the semiconductor substrate opposite the first set of metallization layers.

### Claim 10 (depends on 9)

The method of claim 9, wherein the first die has a first size and the second die has a second size different from the first size.

### Claim 11 (depends on 9)

The method of claim 9, further comprising forming through substrate vias through the semiconductor substrate, wherein the through substrate vias electrically couples the backside redistribution structure to the first set of metallization layers.

### Claim 12 (depends on 9)

The method of claim 9, further comprising attaching a thermal module to the backside redistribution structure opposite the semiconductor substrate.

### Claim 13 (depends on 12)

The method of claim 12, wherein the attaching the thermal module to the backside redistribution structure utilizes a thermal adhesive.

### Claim 14 (depends on 12)

The method of claim 12, further comprising fastening the thermal module to the backside redistribution structure utilizing a screw assembly.

### Claim 15 (depends on 9)

The method of claim 9, further comprising attaching a power module to the second set of metallization layers opposite the first set of metallization layers.

### Claim 16

A method comprising:
forming a first semiconductor die of a first type at least partially within a substrate;
forming a second semiconductor die of a second type at least partially within the substrate, the second type being different from the first type;
forming a third semiconductor die of a third type at least partially within the substrate, the third type being different from the second type;
forming a local interconnect over the first semiconductor die and the second semiconductor die, wherein the local interconnect is in direct physical contact with the first semiconductor die and the second semiconductor die;
forming a semi-global interconnect over the local interconnect, wherein the local interconnect is between the semi-global interconnect and the substrate; and
fastening a thermal module to the substrate with a screw assembly.

### Claim 17 (depends on 16)

The method of claim 16, further comprising attaching a power module to the semi-global interconnect opposite the local interconnect.

### Claim 18 (depends on 16)

The method of claim 16, wherein the fastening the thermal module to the substrate with the screw assembly comprises utilizing a bolt extending through the thermal module, the substrate, the local interconnect, and the semi-global interconnect and fasteners on each end of the bolt to fasten the thermal module.

### Claim 19 (depends on 16)

The method of claim 16, further comprising forming a backside redistribution structure on the substrate opposite the local interconnect.

### Claim 20 (depends on 19)

The method of claim 19, wherein the backside redistribution structure is electrically coupled to the local interconnect by a through substrate via.