# US 12,218,003 B2 · Selective ILD deposition for fully aligned via with airgap

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- Number: US 12,218,003 B2
- Document ID: US12218003B2
- Status: Granted
- Kind: B2
- Application number: 18/139,199
- Filed: 2023-04-25
- Published: 2024-03-21
- Granted: 2025-02-04
- Earliest claimed: 2017-12-11
- Assignees: Adeia Semiconductor Solutions LLC
- Applicants: Adeia Semiconductor Solutions LLC
- Inventors: Christopher J. Penny; Benjamin D. Briggs; Huai Huang; Lawrence A. Clevenger; Michael Rizzolo; Hosadurga Shobha
- Web page: https://patentgrep.com/patent/US12218003B2

## CPC

- H10W 20/46: comprising air gaps
- H10W 20/069: {by forming self-aligned vias or self-aligned contact plugs}
- H10W 20/0693: {by forming self-aligned vias}
- H10W 20/072: {of dielectric parts comprising air gaps}
- H10W 20/075: {of multilayered thin functional dielectric layers}
- H10W 20/076: {in via holes or trenches}
- H10W 20/077: {on sidewalls or on top surfaces of conductors (H10W20/076 takes precedence)}
- H10W 20/084: {for dual-damascene structures}
- H10W 20/085: {involving intermediate temporary filling with material}
- H10W 20/088: {involving partial etching of via holes}
- H10W 20/097: {by thermally treating}
- H10W 20/435: {Cross-sectional shapes or dispositions of interconnections}
- H10W 20/096: {by contacting with gases, liquids or plasmas}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A method is presented forming a fully-aligned via (FAV) and airgaps within a semiconductor device. The method includes forming a plurality of copper (Cu) trenches within an insulating layer, forming a plurality of ILD regions over exposed portions of the insulating layer, selectively removing a first section of the ILD regions in an airgap region, and maintaining a second section of the ILD regions in a non-airgap region. The method further includes forming airgaps in the airgap region and forming a via in the non-airgap region contacting a Cu trench of the plurality of Cu trenches.

## Claims

### Claim 1

A method comprising:
forming trenches within an insulating layer disposed over a semiconductor substrate;
filling the trenches with conductive material to form conductive regions;
selectively forming first dielectric regions on a pattern over exposed top surfaces of the insulating layer;
forming a mask over the semiconductor substrate and removing the first dielectric regions in areas not covered by the mask;
depositing an inter-layer dielectric over remaining first dielectric regions, the conductive regions, and the insulating layer; and
etching a portion of the inter-layer dielectric between two of the remaining first dielectric regions to form a self-aligned via.

### Claim 2 (depends on 1)

The method of claim 1, further comprising:
after removing the first dielectric regions in the areas not covered by the mask, etching exposed regions of the insulating layer disposed between adjacent conductive regions.

### Claim 3 (depends on 2)

The method of claim 2, further comprising,
after etching the exposed regions of the insulating layer disposed between the adjacent conductive regions, depositing the inter-layer dielectric to form at least one airgap between the adjacent conductive regions.

### Claim 4 (depends on 3)

The method of claim 3, further comprising:
after etching the exposed regions of the insulating layer disposed between the adjacent conductive regions, and before depositing the inter-layer dielectric, depositing a dielectric cap on (i) the remaining first dielectric regions, (ii) the conductive regions, and (iii) exposed portions of the insulating layer.

### Claim 5 (depends on 4)

The method of claim 4, further comprising,
after depositing the dielectric cap, depositing the inter-layer dielectric to form at least one airgap between the adjacent conductive regions.

### Claim 6 (depends on 4)

The method of claim 4, wherein the dielectric cap is conformal.

### Claim 7 (depends on 4)

The method of claim 4, wherein the dielectric cap comprises Si and C.

### Claim 8 (depends on 4)

The method of claim 4, wherein the dielectric cap comprises Si and N.

### Claim 9 (depends on 4)

The method of claim 4, wherein the dielectric cap comprises Si, C, and N.

### Claim 10 (depends on 4)

The method of claim 4, wherein the dielectric cap comprises Si, C, B, and N.

### Claim 11 (depends on 4)

The method of claim 4, wherein the dielectric cap comprises multilayers of Si, and one or more of C, B, and N.

### Claim 12 (depends on 4)

The method of claim 4, wherein the dielectric cap lines a portion of the self-aligned via.

### Claim 13 (depends on 1)

The method of claim 1, further comprising:
prior to forming the mask, forming second dielectric regions of the conductive regions and between the first dielectric regions.

### Claim 14 (depends on 13)

The method of claim 13, further comprising:
subsequent to removing the first dielectric regions in the areas not covered by the mask, damaging exposed regions of the insulating layer.

### Claim 15 (depends on 14)

The method of claim 14, wherein damaging the exposed regions of the insulating layer comprises ashing the exposed regions of the insulating layer.

### Claim 16 (depends on 13)

The method of claim 13, further comprising:
prior to depositing the inter-layer dielectric, removing the second dielectric regions.

### Claim 17 (depends on 1)

The method of claim 1, wherein the first dielectric regions comprise Si and O.

### Claim 18 (depends on 1)

The method of claim 1, wherein the first dielectric regions comprise Si, O, and N.

### Claim 19 (depends on 1)

The method of claim 1, wherein the first dielectric regions comprise Si, O, and C.

### Claim 20 (depends on 1)

The method of claim 1, wherein the first dielectric regions comprise Si, O, C, and N.