# US 12,218,001 B2 · Semiconductor package and method of fabricating semiconductor package

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 12,218,001 B2
- Document ID: US12218001B2
- Status: Granted
- Kind: B2
- Application number: 18/504,136
- Filed: 2023-11-07
- Published: 2024-02-29
- Granted: 2025-02-04
- Earliest claimed: 2017-08-28
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Zi-Jheng Liu; Chen-Cheng Kuo; Hung-Jui Kuo
- Web page: https://patentgrep.com/patent/US12218001B2

## CPC

- H10W 20/084: {for dual-damascene structures}
- H10P 14/274: {using seed materials}
- H10P 54/00: Cutting or separating of wafers, substrates or parts of devices
- H10W 20/48: Insulating materials thereof
- H10W 70/611: {for connecting multiple chips together}
- H10W 70/614: {the multiple chips being integrally enclosed}
- H10W 70/635: {Through-vias}
- H10W 74/01: Manufacture or treatment
- H10W 74/129: {forming a chip-scale package [CSP]}
- H10W 20/081: {by forming openings in the dielectric parts}
- H10W 20/082: {the openings being tapered via holes}
- H10W 70/05: of insulating or insulated package substrates, or of interposers, or of redistribution layers (manufacture or treatment of leadframes H10W70/04)
- H10W 70/09: extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs
- H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40)
- H10W 70/654: Top-view layouts
- H10W 72/019: {of bond pads}
- H10W 72/01935: {by plating, e.g. electroless plating or electroplating}
- H10W 72/01938: {in gaseous form, e.g. by CVD or PVD}
- H10W 72/01951: {Changing the shapes of bond pads}
- H10W 72/0198: {batch processes}
- H10W 72/242: {relative to the surface, e.g. recessed, protruding}
- H10W 72/921: {Structures or relative sizes of bond pads}
- H10W 72/922: {Bond pads being integral with underlying chip-level interconnections}
- H10W 72/923: {Bond pads having multiple stacked layers}
- H10W 72/934: {Cross-sectional shape, i.e. in side view}
- H10W 72/9415: {relative to the surface, e.g. recessed, protruding}
- H10W 72/952: {comprising metals or metalloids, e.g. PbSn, Ag or Cu}
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A method of fabricating a semiconductor package includes providing a substrate having at least one contact and forming a redistribution layer on the substrate. The formation of the redistribution layer includes forming a dielectric material layer over the substrate and performing a double exposure process to the dielectric material layer. A development process is then performed and a dual damascene opening is formed in the dielectric material layer. A seed metallic layer is formed over the dual damascene opening and over the dielectric material layer. A metal layer is formed over the seed metallic layer. A redistribution pattern is formed in the first dual damascene opening and is electrically connected with the at least one contact.

## Claims

### Claim 1

A method of forming a semiconductor structure, comprising:
forming at least one contact and a dielectric material layer thereon;
performing a double exposure process to the dielectric material layer including sequentially performing a first exposure process to form first exposure portions in the dielectric material layer and performing a second exposure process to form second exposure portions in the dielectric material layer;
performing a development process to dissolve the first and second exposure portions and over-develop the dielectric material layer to form a dual damascene opening with a first opening wider than the first exposure portion and a second opening wider than the second exposure portion, a bottom size of the first opening is less than a bottom size of the second opening;
forming a seed layer over the dual damascene opening and over the dielectric material layer; and
forming a conductive pattern filled in the dual damascene opening and electrically connected with the at least one contact.

### Claim 2 (depends on 1)

The method as claimed in claim 1, wherein the first exposure portions are formed with a first depth in the dielectric material layer and the second exposure portions are formed with a second depth in the dielectric material layer, and the first depth is larger than the second depth.

### Claim 3 (depends on 2)

The method as claimed in claim 2, wherein locations of the first exposure portions are overlapped with locations of the second exposure portions.

### Claim 4 (depends on 1)

The method as claimed in claim 1, wherein the first exposure process is performed with a first energy dose and the second exposure process is performed with a second energy dose, and the first energy dose is larger than the second energy dose.

### Claim 5 (depends on 1)

The method as claimed in claim 1, wherein the first opening exposes the at least one contact and the second opening is connected with the first opening.

### Claim 6 (depends on 5)

The method as claimed in claim 5, wherein forming a conductive pattern in the dual damascene opening includes forming a first portion located within the first opening and forming a second portion located within the second opening.

### Claim 7 (depends on 1)

The method as claimed in claim 1, wherein forming a conductive pattern comprises forming a metallic layer filling the dual damascene opening, and performing a planarization process to remove the metallic layer and the seed layer outside the dual damascene opening.

### Claim 8

A method of forming an interconnection structure, comprising:
forming contacts and a dielectric material layer covering the contacts;
performing a first exposure process with a first energy dose to form first exposure portions in the dielectric material layer;
performing a second exposure process with a second energy dose to form second exposure portions in the dielectric material layer, wherein the first energy dose is larger than the second energy dose;
performing a development process using a developer solution to remove the first exposure portions respectively and the second exposure portions respectively of the dielectric material layer and over-develop the dielectric material layer in the same development process to form first openings larger than the first exposure portions and second openings larger than the second exposure portions, a bottom size of each of the second openings is greater than a bottom size of each of the first openings;
forming a seed layer over the dielectric material layer and covering the first openings and second openings; and
forming conductive patterns on the seed layer and filled within the first openings and the second openings.

### Claim 9 (depends on 8)

The method as claimed in claim 8, wherein performing the development process further comprising performing a curing process.

### Claim 10 (depends on 8)

The method as claimed in claim 8, wherein the seed layer is formed conformally covering the first openings and the second openings.

### Claim 11 (depends on 10)

The method as claimed in claim 10, wherein the seed layer including titanium and copper is formed by sputtering.

### Claim 12 (depends on 10)

The method as claimed in claim 10, wherein the seed layer is formed to cover the contacts exposed by the first openings.

### Claim 13 (depends on 8)

The method as claimed in claim 8, wherein forming the conductive patterns comprises forming a metal layer filling the first openings and the second openings, and performing a planarization process to remove the metal layer and the seed layer outside the dual damascene opening.

### Claim 14 (depends on 13)

The method as claimed in claim 13, wherein the metal layer including copper is formed by electroplating.

### Claim 15 (depends on 8)

The method as claimed in claim 8, wherein the first exposure portions are formed at locations overlapped with locations of the second exposure portions.

### Claim 16

A method of forming a semiconductor structure, comprising:
forming at least one contact and a dielectric material layer thereon;
performing a double exposure process to the dielectric material layer including sequentially performing a first exposure process to form first exposure portions in the dielectric material layer and performing a second exposure process to form second exposure portions in the dielectric material layer;
performing a development process to dissolve the first and second exposure portions and over-develop the dielectric material layer by removing the dielectric material layer around the first exposure portions and the second exposure portions to form a first opening and a second opening on the first opening, a bottom size of the first opening is less than a bottom size of the second opening;
forming a seed layer into the first opening and the second opening and over the dielectric material layer; and
forming a conductive pattern filled in the first opening and the second opening and electrically connected with the at least one contact.

### Claim 17 (depends on 16)

The method as claimed in claim 16, wherein the first exposure portions are formed with a first depth in the dielectric material layer and the second exposure portions are formed with a second depth in the dielectric material layer, and the first depth is larger than the second depth.

### Claim 18 (depends on 16)

The method as claimed in claim 16, wherein the first exposure process is performed with a first energy dose and the second exposure process is performed with a second energy dose, and the first energy dose is larger than the second energy dose.

### Claim 19 (depends on 16)

The method as claimed in claim 16, wherein forming the conductive pattern comprises forming a metallic layer filling the first opening and the second opening, and performing a planarization process to remove the metallic layer and the seed metallic layer outside the second opening.

### Claim 20 (depends on 16)

The method as claimed in claim 16, wherein performing the development process further comprising performing a curing process.