# US 12,217,999 B2 · Trench isolation process > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,217,999 B2 - Document ID: US12217999B2 - Status: Granted - Kind: B2 - Application number: 17/818,497 - Filed: 2022-08-09 - Published: 2022-12-08 - Granted: 2025-02-04 - Earliest claimed: 2020-10-20 - Assignees: Taiwan Semiconductor Manufacturing Company, Ltd. - Applicants: Taiwan Semiconductor Manufacturing Company, Ltd. - Inventors: Chung-Lei Chen; Cheng-Hsin Chen; Chung Chieh Ting; Che-Yi Lin; Clark Lee - Web page: https://patentgrep.com/patent/US12217999B2 ## CPC - H10W 10/014: {using trench refilling with dielectric materials, e.g. shallow trench isolations} - H10P 14/6903: {containing silicon} - H10P 50/287: {by chemical means} - H10P 52/402: {of semiconductor materials} - H10W 10/17: formed using trench refilling with dielectric materials, e.g. shallow trench isolations - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 - H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10 ## Abstract One or more semiconductor processing tools may form a deep trench within a silicon wafer. The one or more semiconductor processing tools may deposit a first insulating material within the deep trench. The one or more semiconductor processing tools may form, after forming the deep trench with the silicon wafer, a shallow trench above the deep trench. The one or more semiconductor processing tools may deposit a second insulating material within the shallow trench. ## Claims ### Claim 1 A method of providing trench isolation, comprising: performing a deep trench isolation process for a silicon wafer; forming, after performing the deep trench isolation process, a shallow trench having a lower surface that is above a lower surface of a deep trench associated with the deep trench isolation process, wherein an entirety of a first portion of the lower surface of the shallow trench resides below an entirety of a second portion of the lower surface of the shallow trench and is co-planar with a top surface of an entirety of the deep trench; and depositing an insulating material within the shallow trench, wherein a thickness of a first portion of the insulating material that is laterally displaced from the deep trench is greater than a thickness of a second portion of the insulating material that is above the deep trench. ### Claim 2 (depends on 1) The method of claim 1, further comprising: polishing the deep trench and the shallow trench in a same chemical-mechanical polishing process. ### Claim 3 (depends on 1) The method of claim 1, further comprising: forming an active area of the silicon wafer based on forming the shallow trench after performing the deep trench isolation process. ### Claim 4 (depends on 1) The method of claim 1, further comprising: annealing the silicon wafer based on forming the shallow trench after performing the deep trench isolation process. ### Claim 5 (depends on 1) The method of claim 1, further comprising: sealing an upper surface of the deep trench with an oxidation layer based on forming the shallow trench after performing the deep trench isolation process. ### Claim 6 (depends on 1) The method of claim 1, wherein performing the deep trench isolation process comprises: depositing a liner and an insulating material within the deep trench. ### Claim 7 (depends on 1) The method of claim 1, wherein performing the deep trench isolation process comprises: depositing an insulating material within the deep trench. ### Claim 8 A method of providing trench isolation, comprising: performing a deep trench isolation process to form a deep trench having a first depth from an upper surface of a silicon wafer; forming, after performing the deep trench isolation process, a shallow trench having a second depth, from the upper surface of the silicon wafer, that is less than the first depth, wherein the shallow trench has a lower surface comprising a first portion, that is co-planar with an entirety of the deep trench, and a second portion that is on a different plane than the first portion; depositing an insulating material within the shallow trench; and performing a chemical-mechanical polishing process for the deep trench and the shallow trench, wherein a thickness of a first portion of the insulating material that is laterally displaced from the deep trench is greater than a thickness of a second portion of the insulating material that is above the deep trench after performing the chemical-mechanical polishing process, wherein a top surface of the first portion of the insulating material is co-planar with a top surface of the silicon wafer. ### Claim 9 (depends on 8) The method of claim 8, wherein performing the chemical-mechanical polishing process comprises: removing a portion of the insulating material. ### Claim 10 (depends on 8) The method of claim 8, further comprising: forming an active area of the silicon wafer based on performing the chemical-mechanical polishing process. ### Claim 11 (depends on 10) The method of claim 10, further comprising: annealing the silicon wafer based on forming the active area. ### Claim 12 (depends on 8) The method of claim 8, wherein performing the deep trench isolation process comprises: depositing a photoresist layer outside of a region associated with the deep trench; and etching one or more layers within the region associated with the deep trench. ### Claim 13 (depends on 12) The method of claim 12, wherein performing the deep trench isolation process further comprises: etching into the silicon wafer; and removing the photoresist layer. ### Claim 14 A system, comprising: one or more tools configured to: perform a deep trench isolation process for a silicon wafer; form, after a deep trench is formed via the deep trench isolation process, a shallow trench having a lower surface that is above a lower surface of the deep trench; and deposit an insulating material within the shallow trench, wherein a thickness of a first portion of the insulating material that is laterally displaced from the deep trench is greater than a thickness of a second portion of the insulating material that is above the deep trench, wherein at least one of: a top surface of the first portion of the insulating material is co-planar with a top surface of the silicon wafer, or an entirety of a first portion of the lower surface of the shallow trench resides below an entirety of a second portion of the lower surface of the shallow trench and is coplanar with a top surface of an entirety of the deep trench. ### Claim 15 (depends on 14) The system of claim 14, wherein the one or more tools are further configured to: polish the deep trench and the shallow trench in a same chemical-mechanical polishing process. ### Claim 16 (depends on 14) The system of claim 14, wherein the one or more tools are further configured to: form an active area of the silicon wafer based on the shallow trench being formed after the deep trench isolation process. ### Claim 17 (depends on 14) The system of claim 14, wherein the one or more tools are further configured to: anneal the silicon wafer based on the shallow trench being formed after the deep trench isolation process. ### Claim 18 (depends on 14) The system of claim 14, wherein the one or more tools are further configured to: seal an upper surface of the deep trench with an oxidation layer based on the shallow trench being formed after the deep trench isolation process. ### Claim 19 (depends on 14) The system of claim 14, wherein the one or more tools, to perform the deep trench isolation process, are configured to: deposit a liner and an insulating material within the deep trench. ### Claim 20 (depends on 14) The system of claim 14, wherein the one or more tools, to perform the deep trench isolation process, are configured to: deposit an insulating material within the deep trench.