# US 12,217,975 B2 · Semiconductor device having metal gate and poly gate

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- Number: US 12,217,975 B2
- Document ID: US12217975B2
- Status: Granted
- Kind: B2
- Application number: 18/527,151
- Filed: 2023-12-01
- Published: 2024-03-21
- Granted: 2025-02-04
- Earliest claimed: 2019-06-24
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Alexander Kalnitsky; Wei-Cheng Wu; Harry-Hak-Lay Chuang
- Web page: https://patentgrep.com/patent/US12217975B2

## CPC

- H10P 52/403: {of conductive or resistive materials}
- H10D 30/0212: {using self-aligned silicidation}
- H10D 30/0243: {using dummy structures having essentially the same shapes as the semiconductor bodies, e.g. to provide stability}
- H10D 30/0281: {of lateral DMOS [LDMOS] FETs}
- H10D 30/0285: {using formation of insulating sidewall spacers}
- H10D 30/611: {having multiple independently-addressable gate electrodes influencing the same channel (FinFETs having multiple distinct gate electrodes H10D30/6215; multi-gate TFT H10D30/6733)}
- H10D 30/65: Lateral DMOS [LDMOS] FETs
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 64/661: {the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon having vertical doping variation (having lateral variation in the gate structure H10D64/671)}
- H10D 84/014: {the gate conductors having different materials or different implants}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/83: of only insulated-gate FETs [IGFET]
- H10D 84/83125: {the IGFETs characterised by having shared source or drain regions}
- H10D 84/835: {comprising LDMOS}
- H10D 84/83138: {the IGFETs characterised by having different shapes or dimensions of their gate conductors}
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A semiconductor device includes a substrate, a first well, a second well, a metal gate, a poly gate, a source region, and a drain region. The first well and the second well are within the substrate. The metal gate is partially over the first well. The poly gate is over the second well. The poly gate is separated from the metal gate, and a width ratio of the poly gate to the metal gate is in a range from about 0.1 to about 0.2. The source region and the drain region are respectively within the first well and the second well.

## Claims

### Claim 1

A method of fabricating a semiconductor device, comprising:
forming shallow trench isolation (STI) structures in a substrate;
forming a dummy gate stack and a poly gate stack over the substrate, wherein the dummy gate stack has a lateral dimension wider than a lateral dimension of the poly gate stack;
forming a source region between the dummy gate stack and a first one of the STI structures;
forming a drain region between the poly gate stack and a second one of the STI structures;
after forming the drain region between the poly gate stack and the second one of the STI structures, conformally depositing an oxide material layer over the substrate, the dummy gate stack and the poly gate stack;
patterning the oxide material layer; and
replacing the dummy gate stack with a metal gate stack, wherein the metal gate stack has a lateral dimension wider than the lateral dimension of the poly gate stack.

### Claim 2 (depends on 1)

The method of claim 1, wherein a distance between the metal gate stack and the poly gate stack is in a range from about 0.1 μm to about 1 μm.

### Claim 3 (depends on 1)

The method of claim 1, wherein patterning the oxide material layer is performed such that the oxide material layer remains between the dummy gate stack and the poly gate stack.

### Claim 4 (depends on 1)

The method of claim 1, wherein patterning the oxide material layer is performed such that the oxide material layer extends over a top surface of the dummy gate stack and along a sidewall of the dummy gate stack.

### Claim 5 (depends on 1)

The method of claim 1, wherein patterning the oxide material layer is performed such that the oxide material layer extends over a top surface of the poly gate stack and along a sidewall of the poly gate stack.

### Claim 6 (depends on 1)

The method of claim 1, further comprising:
after patterning the oxide material layer, performing a silicidation process to a surface of the substrate exposed by the oxide material layer.

### Claim 7 (depends on 1)

The method of claim 1, further comprising:
after patterning the oxide material layer, performing a silicidation process to form a first silicide region on the drain region and a second silicide region on the source region.

### Claim 8 (depends on 7)

The method of claim 7, wherein the silicidation process is performed prior to replacing the dummy gate stack with the metal gate stack.

### Claim 9 (depends on 1)

The method of claim 1, wherein the dummy gate stack, the poly gate stack and the STI structures are arranged along a direction, the dummy gate stack has a lateral dimension along the direction wider than a lateral dimension of the poly gate stack along the direction.

### Claim 10

A method of fabricating a semiconductor device, comprising:
forming a first well and a second well in a substrate, wherein the first well and the second well include different types of dopants, and the first well is a neighbor to the second well;
forming a dummy gate stack and a poly gate stack on the substrate, wherein the dummy gate stack and the poly gate stack are physically separated from each other;
forming a source region adjacent to the dummy gate stack, wherein the source region is in the first well;
forming a drain region adjacent to the poly gate stack, wherein the drain region is in the second well; and
replacing the dummy gate stack with a metal gate stack, wherein the metal gate stack overlaps the first well and the second well, and the poly gate stack overlaps the second well and does not overlap the first well.

### Claim 11 (depends on 10)

The method of claim 10, wherein the poly gate stack is between the metal gate stack and the drain region.

### Claim 12 (depends on 10)

The method of claim 10, wherein the poly gate stack is between the first well and the drain region.

### Claim 13 (depends on 10)

The method of claim 10, wherein the metal gate stack is between the source region and the poly gate stack.

### Claim 14 (depends on 10)

The method of claim 10, further comprising:
after forming the drain region, forming an oxide layer between the dummy gate stack and the poly gate stack;
forming an etch stop layer lining the oxide layer; and
forming an interlayer dielectric layer covering the etch stop layer.

### Claim 15 (depends on 14)

The method of claim 14, wherein forming the oxide layer comprises:
forming the oxide layer exposing the source region and the drain region.

### Claim 16 (depends on 14)

The method of claim 14, wherein the oxide layer is in contact with the second well.

### Claim 17

A method of fabricating a semiconductor device, comprising:
forming a first well and a second well in a substrate, wherein the first well and the second well include different types of dopants, and the first well is a neighbor to the second well;
forming a dummy gate stack and a poly gate stack on the substrate, wherein the dummy gate stack is on the first well and the second well, and the poly gate stack is on the second well and is discontinuous from the dummy gate stack;
forming a source region adjacent to the dummy gate stack, wherein the source region is in the first well;
forming a drain region adjacent to the poly gate stack, wherein the drain region is in the second well;
depositing a hard mask on the poly gate stack, wherein the hard mask is made of polymer or metal; and
after depositing the hard mask on the poly gate stack, replacing the dummy gate stack with a metal gate stack.

### Claim 18 (depends on 17)

The method of claim 17, further comprising:
removing the hard mask after replacing the dummy gate stack with the metal gate stack.

### Claim 19 (depends on 17)

The method of claim 17, wherein replacing the dummy gate stack comprises:
performing a planarization process to remove the dummy gate stack and the hard mask.

### Claim 20 (depends on 17)

The method of claim 17, wherein depositing the hard mask on the poly gate stack comprises:
forming the hard mask with a width larger than two times a width of the poly gate stack.