# US 12,217,971 B2 · Method for forming semiconductor device

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- Number: US 12,217,971 B2
- Document ID: US12217971B2
- Status: Granted
- Kind: B2
- Application number: 17/391,660
- Filed: 2021-08-02
- Published: 2022-10-06
- Granted: 2025-02-04
- Earliest claimed: 2021-03-31
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Ching-Yu Chang; Jei-Ming Chen; Tze-Liang Lee
- Web page: https://patentgrep.com/patent/US12217971B2

## CPC

- H10P 50/73: {using masks for insulating materials}
- H10P 76/405: {characterised by their composition, e.g. multilayer masks}
- H10P 76/4085: {characterised by the processes involved to create the masks}
- H10W 20/089: {using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning}
- H10W 20/43: Layouts of interconnections
- H10D 84/0149: {Manufacturing their interconnections or electrodes, e.g. source or drain electrodes}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10P 14/6336: {in the presence of a plasma [PECVD]}
- H10P 14/6339: {deposition by cyclic CVD, e.g. ALD, ALE or pulsed CVD}
- H10P 14/69394: {the material containing titanium, e.g. TiO2}
- H10W 20/081: {by forming openings in the dielectric parts}
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A method includes forming a dielectric layer over a substrate; forming a patterned amorphous silicon layer over a dielectric layer; depositing a first spacer layer over the patterned amorphous silicon layer; depositing a second spacer layer over the first spacer layer; forming a photoresist having an opening over the substrate; depositing a hard mask layer in the opening of the photoresist; after depositing the hard mask layer in the opening of the photoresist, removing the photoresist; and performing an etching process to etch the dielectric layer by using the patterned amorphous silicon layer, the first spacer layer, the second spacer layer, and the hard mask layer as an etch mask, in which the etching process etches the second spacer layer at a slower etch rate than etching the first spacer layer.

## Claims

### Claim 1

A method, comprising:
forming a dielectric layer over a substrate;
forming a patterned amorphous silicon layer over the dielectric layer;
depositing a first spacer layer over the patterned amorphous silicon layer;
depositing a second spacer layer over the first spacer layer;
forming a photoresist having an opening over the substrate;
depositing a hard mask layer in the opening of the photoresist;
etching back the hard mask layer to lower a top surface of the hard mask layer to a position lower than a top surface of the second spacer layer;
after depositing the hard mask layer in the opening of the photoresist, removing the photoresist; and
performing an etching process to etch the dielectric layer by using the patterned amorphous silicon layer, the first spacer layer, the second spacer layer, and the hard mask layer as an etch mask, wherein the etching process etches the second spacer layer at a slower etch rate than etching the first spacer layer.

### Claim 2 (depends on 1)

The method of claim 1, further comprising:
after removing the photoresist and prior to etching the dielectric layer, performing an anisotropic etching process to remove first horizontal portions of the first spacer layer and the second spacer layer, while leaving second horizontal portions of the first spacer layer and the second spacer layer under the hard mask layer.

### Claim 3 (depends on 1)

The method of claim 1, wherein the photoresist is formed after depositing the second spacer layer over the first spacer layer.

### Claim 4 (depends on 1)

The method of claim 1, wherein the first spacer layer and the second spacer layer are made of titanium oxide.

### Claim 5 (depends on 1)

The method of claim 1, wherein the first spacer layer is deposited using a plasma-free deposition process, while the second spacer layer is deposited using plasma-treatment, and the first spacer layer and the second spacer layer are made of a same material.

### Claim 6

A method, comprising:
forming a dielectric layer over a substrate;
forming a patterned amorphous silicon layer over the dielectric layer;
depositing a first spacer layer over the patterned amorphous silicon layer;
depositing a second spacer layer over the first spacer layer to form a bilayer spacer film including the first spacer layer and the second spacer layer;
forming a hard mask covering a first horizontal portion of the bilayer spacer film, wherein a top surface of the hard mask is lower than a topmost position of the bilayer spacer film;
performing an etching process to remove a second horizontal portion of the bilayer spacer film not covered by the hard mask, wherein the first horizontal portion of the bilayer spacer film and a vertical portion of the bilayer spacer film along a sidewall of the patterned amorphous silicon layer remain after the etching process is complete; and
etching the dielectric layer by using the remaining first horizontal portion and vertical portion of the bilayer spacer film and the hard mask as an etch mask.

### Claim 7 (depends on 6)

The method of claim 6, wherein forming the hard mask comprises:
forming a photoresist having an opening over the second spacer layer;
depositing a hard mask layer in the opening in the photoresist; and
etching back the hard mask layer.

### Claim 8 (depends on 6)

The method of claim 6, further comprising:
after performing the etching process to remove the second horizontal portion of the bilayer spacer film, forming a photoresist having an opening exposing a portion of the patterned amorphous silicon layer; and
etching the exposed portion of the patterned amorphous silicon layer.

### Claim 9 (depends on 6)

The method of claim 6, wherein the hard mask is separated from the first spacer layer by the second spacer layer.

### Claim 10 (depends on 6)

The method of claim 6, wherein the second spacer layer is in contact with sidewalls and a bottom surface of the hard mask.

### Claim 11 (depends on 6)

The method of claim 6, wherein the first spacer layer and the second spacer layer are made of titanium oxide.

### Claim 12

A method, comprising:
forming a dielectric layer over a substrate;
forming a patterned amorphous silicon layer over the dielectric layer;
depositing a first spacer layer over the patterned amorphous silicon layer;
depositing a second spacer layer over the first spacer layer, wherein the first spacer layer and the second spacer layer are made of titanium oxide;
forming a hard mask layer over a first portion of the second spacer layer, while leaving a second portion of the second spacer layer uncovered by the hard mask layer; and
performing an etching process to etch the dielectric layer by using the patterned amorphous silicon layer, the first spacer layer, the second spacer layer, and the hard mask layer as an etch mask.

### Claim 13 (depends on 12)

The method of claim 12, wherein a top surface of the hard mask layer is lower than a top surface of the second spacer layer.

### Claim 14 (depends on 12)

The method of claim 12, further comprising:
forming a photoresist having an opening over the second spacer layer, wherein the opening of the photoresist exposes the first portion of the second spacer layer and the photoresist covers the second portion of the second spacer layer, wherein the hard mask layer is formed in the opening of the photoresist; and
removing the photoresist after forming the hard mask layer.

### Claim 15 (depends on 14)

The method of claim 14, further comprising, prior to removing the photoresist, etching back the hard mask layer to lower a top surface of the hard mask layer.

### Claim 16 (depends on 12)

The method of claim 12, wherein an entirety of the hard mask layer is spaced apart from the first spacer layer.

### Claim 17 (depends on 12)

The method of claim 12, further comprising, prior to performing the etching process, removing first horizontal portions of the first spacer layer and the second spacer layer that are not covered by the hard mask layer.

### Claim 18 (depends on 17)

The method of claim 17, wherein second horizontal portions of the first spacer layer and the second spacer layer under the hard mask layer remain during performing the etching process.

### Claim 19 (depends on 12)

The method of claim 12, wherein the first spacer layer is deposited using a plasma-free deposition process, while the second spacer layer is deposited using plasma-treatment.

### Claim 20 (depends on 12)

The method of claim 12, wherein the etching process etches the second spacer layer at a slower etch rate than etching the first spacer layer.