# US 12,217,962 B2 · Semiconductor manufacturing system, method of manufacturing a semiconductor device, and semiconductor device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,217,962 B2 - Document ID: US12217962B2 - Status: Granted - Kind: B2 - Application number: 17/459,400 - Filed: 2021-08-27 - Published: 2022-03-17 - Granted: 2025-02-04 - Earliest claimed: 2020-09-15 - Assignees: Kioxia Corporation - Applicants: Kioxia Corporation - Inventors: Shingo Honda - Web page: https://patentgrep.com/patent/US12217962B2 ## CPC - H10P 76/4088: {Processes for improving the resolution of the masks} - G03F 7/162: {Coating on a rotating support, e.g. using a whirler or a spinner} - G03F 7/70425: {Imaging strategies, e.g. for increasing throughput or resolution, printing product fields larger than the image field or compensating lithography- or non-lithography errors, e.g. proximity correction, mix-and-match, stitching or double patterning} - G03F 7/70525: {Controlling normal operating mode, e.g. matching different apparatus, remote control or prediction of failure} - H01J 37/32642: {Focus rings} - H10P 50/283: {by chemical means} - H10P 50/285: {of materials not containing Si, e.g. PZT or Al2O3} - H10P 50/73: {using masks for insulating materials} - H10P 76/2041: {Photolithographic processes} - H10W 20/082: {the openings being tapered via holes} - H10W 20/089: {using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning} - H10W 20/42: Vias, e.g. via plugs - H10W 20/435: {Cross-sectional shapes or dispositions of interconnections} - H01J 2237/3341: Reactive etching - H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10 - G03F: PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR; (phototypographic composing devices B41B; photosensitive materials or processes for photographic purposes G03C; electrophotography, sensitive layers or processes therefor G03G) - H01J: ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS (spark-gaps H01T; electric arc lamps H05B31/00; particle accelerators H05H) - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract A semiconductor manufacturing system includes a calculation unit that calculates an inclination degree of an incidence direction of an etchant in an etching device according to a worn state of a part of the etching device. A correction unit corrects a second exposure pattern so that an edge position in the second exposure pattern including an edge is shifted from a first exposure pattern according to the calculated inclination degree. An exposure device exposes a second resist film formed on the substrate from which a first resist pattern is removed with the second exposure pattern. A development device develops the second resist film and forms a second resist pattern on the substrate. The etching device performs etching processing on the substrate by using the second resist pattern as a mask. ## Claims ### Claim 1 A method of manufacturing a semiconductor device, the method comprising: depositing an insulating film on a substrate; depositing a first mask film on or over the insulating film; depositing a hard mask film on the insulating film after the insulating film is deposited and before the first mask film is deposited; depositing a second mask film on the first mask film; forming a first resist pattern on the second mask film; processing the second mask film by using the first resist pattern as a mask to form a second mask pattern including an edge; forming a second resist pattern wherein an edge position is shifted from the first resist pattern on the second mask pattern, from which the first resist pattern is removed; processing the first mask film using the second resist pattern and the second mask pattern as masks, to form a first mask pattern, the first mask pattern having an inclination angle of a side surface of a first side larger than an inclination angle of a side surface of a second side as seen in a cross-sectional view; processing the hard mask film using the second resist pattern, the second mask pattern, and the first mask pattern as masks to form a third mask pattern, the third mask pattern having the inclination angle of the side surface of the first side larger than the inclination angle of the side surface of the second side in the cross-sectional view; processing the insulating film using the first mask pattern as a mask to form a pattern, the pattern having the inclination angle of the side surface of the first side equal to the inclination angle of the side surface of the second side as seen in a cross-sectional view; and wherein the forming of the pattern includes processing the insulating film using the first mask pattern and the third mask pattern as masks to form the pattern. ### Claim 2 (depends on 1) The method of manufacturing the semiconductor device according to claim 1, wherein the substrate includes a plurality of shot areas, and the forming of the second resist pattern includes forming the second resist pattern, on the second mask pattern, in which the edge position is shifted from the first resist pattern by a direction and an amount determined according to a position of the shot areas on the substrate. ### Claim 3 (depends on 1) The method of manufacturing the semiconductor deVice according to claim 1, wherein the first mask film includes spin on carbon. ### Claim 4 (depends on 1) The method of manufacturing the semiconductor deVice according to claim 1, wherein the second mask film includes spin on glass.