# US 12,217,961 B2 · Hard mask trimming in method for manufacturing semiconductor device

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- Number: US 12,217,961 B2
- Document ID: US12217961B2
- Status: Granted
- Kind: B2
- Application number: 17/856,376
- Filed: 2022-07-01
- Published: 2024-01-04
- Granted: 2025-02-04
- Earliest claimed: 2022-07-01
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Chia-Chien Kuang; Tze-Chung Lin; Li-Te Lin
- Web page: https://patentgrep.com/patent/US12217961B2

## CPC

- H10P 76/4085: {characterised by the processes involved to create the masks}
- H10D 30/014: {of FETs having zero-dimensional [0D] or one-dimensional [1D] channels, e.g. quantum wire FETs, single-electron transistors [SET] or Coulomb blockade transistors}
- H10D 30/019: {of FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 30/031: {of thin-film transistors [TFT]}
- H10D 30/501: {FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 62/121: {oriented parallel to substrates}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10P 50/285: {of materials not containing Si, e.g. PZT or Al2O3}
- H10P 50/695: {characterised by the process involved to create the mask, e.g. lift-off masks or sidewalls or to modify the mask}
- H10P 70/23: {during, before or after processing of insulating materials}
- B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
- H10P 50/692: {characterised by their composition, e.g. multilayer masks or materials}
- H10P 76/405: {characterised by their composition, e.g. multilayer masks}
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES

## Abstract

A method for manufacturing a semiconductor device includes: forming a patterned hard mask on a patterned structure disposed on a substrate, such that a hard mask portion of the patterned hard mask is disposed on a fin portion of the patterned structure; and laterally trimming the hard mask portion by a lateral etching process. The lateral etching process includes a radical etching process and a chemical etching process. Alternatively, the lateral etching process includes a radical etching process, a plasma etching process, or a combination thereof, and a cleaning process.

## Claims

### Claim 1

A method for manufacturing a semiconductor device, comprising:
forming a patterned hard mask on a patterned structure disposed on a substrate, such that a hard mask portion of the patterned hard mask is disposed on a fin portion of the patterned structure; and
laterally trimming the hard mask portion by a lateral etching process which includes a radical etching process and a chemical etching process.

### Claim 2 (depends on 1)

The method according to claim 1, wherein the radical etching process is conducted using an etching gas including a fluoride gas and a hydrogen gas.

### Claim 3 (depends on 1)

The method according to claim 1, wherein the chemical etching process is conducted using an etching gas including a chloride gas.

### Claim 4 (depends on 1)

The method according to claim 1, wherein the radical etching process and the chemical etching process are conducted at a temperature ranging from 200° C. to 500° C.

### Claim 5 (depends on 1)

The method according to claim 1, wherein the radical etching process is conducted at a power ranging from 250 W to 500 W.

### Claim 6 (depends on 1)

The method according to claim 1, wherein the radical etching process is conducted at a pressure ranging from 2000 mTorr to 5000 mTorr.

### Claim 7 (depends on 1)

The method according to claim 1, wherein the chemical etching process is conducted at a pressure ranging from 2000 mTorr to 24000 mTorr.

### Claim 8 (depends on 1)

The method according to claim 1, wherein the radical etching process is conducted at a flow rate of the fluoride gas ranging from 15 sccm to 200 sccm and a flow rate of the hydrogen gas ranging from 1000 sccm to 2400 sccm.

### Claim 9 (depends on 1)

The method according to claim 1, wherein the chemical etching process is conducted at a flow rate of the chloride gas ranging from 200 sccm to 500 sccm.

### Claim 10

A method for manufacturing a semiconductor device, comprising:
forming a patterned hard mask on a patterned structure disposed on a substrate, such that a hard mask portion of the patterned hard mask is disposed on a fin portion of the patterned structure; and
laterally trimming the hard mask portion by a lateral etching process which includes a radical etching process, a plasma etching process, or a combination thereof, and a cleaning process.

### Claim 11 (depends on 10)

The method according to claim 10, wherein the radical etching process, the plasma etching process, or the combination thereof is conducted using an etching gas including a chloride gas.

### Claim 12 (depends on 10)

The method according to claim 10, wherein the cleaning process is conducted using an oxygen gas.

### Claim 13 (depends on 10)

The method according to claim 10, wherein the radical etching process, the plasma etching process, or the combination thereof is conducted at a temperature ranging from 50° C. to 130° C.

### Claim 14 (depends on 10)

The method according to claim 10, wherein the plasma etching process and the cleaning process are conducted at a power ranging from 250 W to 1000 W.

### Claim 15 (depends on 10)

The method according to claim 10, wherein the plasma etching process and the cleaning process are conducted at a pressure ranging from 1 mTorr to 10 mTorr.

### Claim 16 (depends on 10)

The method according to claim 10, wherein the plasma etching process is conducted at flow rate of the chloride gas ranging from 50 sccm to 200 sccm.

### Claim 17 (depends on 10)

The method according to claim 10, wherein the cleaning process is conducted at flow rate of the oxygen gas ranging from 25 sccm to 100 sccm.

### Claim 18

A method for manufacturing a semiconductor device, comprising:
forming a patterned hard mask on a patterned structure disposed on a substrate, such that a hard mask portion of the patterned hard mask is disposed on a fin portion of the patterned structure; and
laterally trimming the hard mask portion by a lateral etching process, such that the hard mask portion trimmed by the lateral etching process has a lateral etch amount ranging from 2 nm to 7 nm.

### Claim 19 (depends on 18)

The method according to claim 18, wherein the hard mask portion trimmed by the lateral etching process has a top lost amount ranging from 0 nm to 5 nm.

### Claim 20 (depends on 18)

The method according to claim 18, wherein the hard mask portion trimmed by the lateral etching process has a sidewall roughness ranging from 0 nm to 2 nm.