# US 12,217,957 B2 · Engineered substrate structures for power and RF applications

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 12,217,957 B2
- Document ID: US12217957B2
- Status: Granted
- Kind: B2
- Application number: 18/104,148
- Filed: 2023-01-31
- Published: 2023-06-08
- Granted: 2025-02-04
- Earliest claimed: 2016-06-14
- Assignees: QROMIS, Inc.
- Applicants: QROMIS, Inc.
- Inventors: Vladimir Odnoblyudov; Cem Basceri; Shari Farrens
- Web page: https://patentgrep.com/patent/US12217957B2

## CPC

- H10P 14/2921: {being crystalline insulating materials}
- C23C 16/24: Deposition of silicon only
- C23C 16/303: {Nitrides}
- C23C 16/345: {Silicon nitride}
- C30B 25/18: characterised by the substrate
- C30B 29/06: Silicon
- C30B 29/406: {Gallium nitride}
- C30B 29/68: Crystals with laminate structure, e.g. "superlattices"
- C30B 33/06: Joining of crystals
- C30B 33/08: Etching
- H10D 62/8503: {Nitride Group III-V materials, e.g. AlN or GaN}
- H10D 84/05: using Group III-V technology
- H10P 14/2924: {Structures}
- H10P 14/3211: {Silicon, silicon germanium or germanium}
- H10P 14/3238: {being insulating materials}
- H10P 14/3241: {being conductive materials}
- H10P 14/3251: {consisting of three or more layers}
- H10P 14/3411: {Silicon, silicon germanium or germanium}
- H10P 14/3416: {Nitrides}
- H10W 20/021: {of interconnections within wafers or substrates}
- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10D 30/4732: {using Group III-V semiconductor material}
- H10D 30/801: {FETs having heterojunction gate electrodes}
- H10P 90/1916: {with separation or delamination along an ion implanted layer, e.g. Smart-cut}
- H10W 10/181: {Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers}
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- C23C: COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL (making metal-coated products by extrusion B21C23/22; covering with metal by connecting pre-existing layers to articles, see the relevant places, e.g. B21D39/00, B23K; metallising of glass C03C; metallising mortars, concrete, artificial stone, ceramics or natural stone C04B41/00; enamelling of, or applying a vitreous layer to, metals C23D; treating metal surfaces or coating of metals by electrolysis or electrophoresis C25D; single-crystal film growth C30B; by metallising textiles D06M11/83; decorating textiles by locally metallising D06Q1/04)
- C30B: SINGLE-CRYSTAL GROWTH (by using ultra-high pressure, e.g. for the formation of diamonds, B01J3/06); UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL (zone-refining of metals or alloys C22B); PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE (casting of metals, casting of other substances by the same processes or devices B22D; working of plastics B29; modifying the physical structure of metals or alloys C21D, C22F); SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE (for producing semiconductor devices or parts thereof H10); APPARATUS THEREFOR
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A substrate includes a support structure comprising a polycrystalline ceramic core, a first adhesion layer encapsulating the polycrystalline ceramic core, a barrier layer encapsulating the first adhesion layer, a second adhesion layer coupled to the barrier layer, and a conductive layer coupled to the second adhesion layer. The substrate also includes a bonding layer coupled to the support structure, a substantially single crystal silicon layer coupled to the bonding layer, and an epitaxial semiconductor layer coupled to the substantially single crystal silicon layer.

## Claims

### Claim 1

A substrate comprising:
a support structure comprising:
a polycrystalline ceramic core;
a first adhesion layer encapsulating the polycrystalline ceramic core;
a conductive layer coupled to the first adhesion layer;
a second adhesion layer coupled to the conductive layer;
a barrier layer encapsulating the first adhesion layer;
the second adhesion layer coupled to the barrier layer; and
the conductive layer coupled to the second adhesion layer;
a bonding layer coupled to the support structure;
a substantially single crystal silicon layer coupled to the bonding layer;
an epitaxial semiconductor layer coupled to the substantially single crystal silicon layer; and
an epitaxial III-V layer coupled to the epitaxial semiconductor layer.

### Claim 2 (depends on 1)

The substrate of claim 1 wherein the polycrystalline ceramic core comprises aluminum nitride.

### Claim 3 (depends on 1)

The substrate of claim 1 wherein the bonding layer comprises silicon oxide.

### Claim 4 (depends on 1)

The substrate of claim 1 wherein the epitaxial semiconductor layer comprises a III-V material.

### Claim 5 (depends on 4)

The substrate of claim 4 wherein the epitaxial III-V layer comprises an epitaxial gallium nitride layer.

### Claim 6 (depends on 5)

The substrate of claim 5 wherein the epitaxial gallium nitride layer has a thickness of about 5 μm or greater.

### Claim 7 (depends on 1)

The substrate of claim 1 wherein the epitaxial semiconductor layer comprises an epitaxial single crystal silicon layer.

### Claim 8 (depends on 7)

The substrate of claim 7 further comprising a plurality of vias passing from the epitaxial III-V layer to the epitaxial single crystal silicon layer.

### Claim 9 (depends on 1)

The substrate of claim 1 wherein the substantially single crystal silicon layer comprises an exfoliated silicon layer.

### Claim 10 (depends on 1)

The substrate of claim 1 wherein the substantially single crystal silicon layer comprises an exfoliated silicon layer and an epitaxial silicon layer grown on the exfoliated silicon layer, and the substantially single crystal silicon layer has a thickness of about 0.5 μm.

### Claim 11 (depends on 1)

The substrate of claim 1 wherein:
the first adhesion layer comprises a first tetraethyl orthosilicate (TEOS) layer encapsulating the polycrystalline ceramic core;
the barrier layer comprises a silicon nitride layer;
the second adhesion layer comprises a second TEOS layer; and
the conductive layer comprises a polysilicon layer.