# US 12,217,822 B2 · Memory device with source line control

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- Number: US 12,217,822 B2
- Document ID: US12217822B2
- Status: Granted
- Kind: B2
- Application number: 18/232,542
- Filed: 2023-08-10
- Published: 2023-11-30
- Granted: 2025-02-04
- Earliest claimed: 2022-01-25
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Perng-Fei Yuh; Yih Wang
- Web page: https://patentgrep.com/patent/US12217822B2

## CPC

- G11C 7/1096: {Write circuits, e.g. I/O line write drivers}
- G11C 13/0069: {Writing or programming circuits or methods}
- G11C 7/1069: {I/O lines read out arrangements}
- G11C 7/12: Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
- G11C 8/08: Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
- G11C 11/1655: {Bit-line or column circuits}
- G11C 11/1657: {Word-line or row circuits}
- G11C 11/1659: {Cell access}
- G11C 11/1673: {Reading or sensing circuits or methods}
- G11C 11/1675: {Writing or programming circuits or methods}
- G11C 11/1693: {Timing circuits or methods}
- G11C 13/0026: {Bit-line or column circuits}
- G11C 13/0028: {Word-line or row circuits}
- G11C 13/003: {Cell access}
- G11C 13/004: {Reading or sensing circuits or methods}
- G11C 13/0061: {Timing circuits or methods}
- G11C 17/16: using electrically-fusible links
- G11C 11/165: {Auxiliary circuits}
- G11C 11/221: {using ferroelectric capacitors}
- G11C 11/2255: {Bit-line or column circuits}
- G11C 11/2257: {Word-line or row circuits}
- G11C 11/2259: {Cell access}
- G11C 11/2273: {Reading or sensing circuits or methods}
- G11C 11/2275: {Writing or programming circuits or methods}
- G11C 11/2293: {Timing circuits or methods}
- G11C 11/407: for memory cells of the field-effect type
- G11C 17/18: Auxiliary circuits, e.g. for writing into memory
- G11C 2213/79: Array wherein the access device being a transistor
- G11C 2213/82: Array having, for accessing a cell, a word line, a bit line and a plate or source line receiving different potentials
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

Disclosed herein are related to a memory device including a set of memory cells and a memory controller. In one aspect, each of the set of memory cells includes a select transistor and a storage element connected in series between a corresponding bit line and a corresponding source line. In one aspect, the memory controller is configured to apply a first write voltage to a bit line coupled to a selected memory cell, apply a second write voltage to a word line coupled to a gate electrode of a select transistor of the selected memory cell during a first time period, and apply a third write voltage to a source line coupled to the selected memory cell. The second write voltage may be between the first write voltage and the third write voltage.

## Claims

### Claim 1

A memory system, comprising:
a memory cell comprising a select transistor corresponding to a bit line and a word line; and
a memory controller coupled to the memory cell, the memory controller to:
apply a first write voltage to the bit line during a first time period to write data to the memory cell; and
apply a second write voltage to the word line coupled to the memory cell during the first time period,
wherein a difference between the first write voltage and the second write voltage is less than an allowable stress voltage of the select transistor, wherein the second write voltage is between the first write voltage and a third write voltage of a source line coupled to the memory cell.

### Claim 2 (depends on 1)

The memory system of claim 1, wherein the memory controller is to apply the third write voltage to the source line coupled to the memory cell during the first time period.

### Claim 3 (depends on 1)

The memory system of claim 1, wherein a second difference between the second write voltage and the third write voltage is less than the allowable stress voltage of the select transistor.

### Claim 4 (depends on 1)

The memory system of claim 1, wherein the memory controller is to:
apply the second write voltage to a second bit line coupled to a second memory cell during the first time period, the second memory cell coupled to the source line, and
apply the second write voltage to a second word line coupled to a second gate electrode of a second select transistor of the second memory cell during the first time period.

### Claim 5 (depends on 1)

The memory system of claim 1, wherein the memory controller is to:
apply a first read voltage to the bit line coupled to the memory cell during a second time period; and
apply a second read voltage to the source line coupled to the memory cell during the second time period.

### Claim 6 (depends on 5)

The memory system of claim 5, wherein the memory controller is to:
apply a third read voltage to the word line coupled to a gate electrode of the memory cell during the second time period, the first read voltage between the second read voltage and the third read voltage.

### Claim 7 (depends on 5)

The memory system of claim 5, wherein the memory controller is to:
apply the first read voltage to a second bit line coupled to a second memory cell during the second time period, the second memory cell coupled to a second source line, and
apply the first read voltage to a second word line coupled to a second gate electrode of the second memory cell during the second time period.

### Claim 8 (depends on 1)

The memory system of claim 1, wherein the memory cell further comprises a storage element.

### Claim 9 (depends on 8)

The memory system of claim 8, wherein the storage element comprises a magnetic tunnel junction (MTJ) cell.

### Claim 10 (depends on 8)

The memory system of claim 8, wherein the storage element comprises a metal-insulator-metal (MIM) capacitor.

### Claim 11 (depends on 1)

The memory system of claim 1, wherein the word line is coupled to a gate of the select transistor and extends in parallel with the bit line along a first direction.

### Claim 12 (depends on 11)

The memory system of claim 11, wherein the source line extends perpendicular to the word line along a second direction.

### Claim 13

A memory system:
a memory array including:
a first memory cell;
a second memory cell;
a first bit line coupled to the first memory cell and the second memory cell; and
a first word line coupled to the first memory cell and the second memory cell; and
a memory controller to:
apply a first write voltage to the first bit line during a first time period to write data to the first memory cell; and
apply a second write voltage to the first word line coupled to the first memory cell during the first time period,
wherein a difference between the first write voltage and the second write voltage is less than an allowable stress voltage of a select transistor of the first memory cell, wherein the second write voltage is between the first write voltage and a third write voltage of a source line coupled to the first memory cell.

### Claim 14 (depends on 13)

The memory system of claim 13, wherein the memory controller is to apply the third write voltage to the source line during the first time period.

### Claim 15 (depends on 13)

The memory system of claim 13, wherein the memory controller is to:
apply a first read voltage to the first bit line coupled to the first memory cell during a second time period; and
apply a second read voltage to the source line coupled to the first memory cell during the second time period.

### Claim 16 (depends on 15)

The memory system of claim 15, wherein the memory controller is to:
apply a third read voltage to the first word line during the second time period, the first read voltage between the second read voltage and the third read voltage.

### Claim 17 (depends on 13)

The memory system of claim 13, wherein the memory controller is to:
apply the third write voltage to a second source line coupled to the second memory cell during the first time period.

### Claim 18

A method, comprising:
applying, by a memory controller, a first write voltage to a bit line during a time period to write data to a selected memory cell, the bit line coupled to the selected memory cell and an unselected memory cell; and
applying, by the memory controller, a second write voltage to a first word line coupled to the selected memory cell during the time period,
wherein a difference between the first write voltage and the second write voltage is less than an allowable stress voltage of a select transistor of the selected memory cell, wherein the second write voltage is between the first write voltage and a third write voltage of a source line coupled to the selected memory cell.

### Claim 19 (depends on 18)

The method of claim 18, further comprising:
applying, by the memory controller, the third write voltage to the source line coupled to the selected memory cell during the time period.