# US 12,217,821 B2 · Storage device and operating method with multiple channels > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,217,821 B2 - Document ID: US12217821B2 - Status: Granted - Kind: B2 - Application number: 17/831,969 - Filed: 2022-06-03 - Published: 2023-07-27 - Granted: 2025-02-04 - Earliest claimed: 2022-01-25 - Assignees: SK hynix Inc. - Applicants: SK hynix Inc. - Inventors: Seung Han Ryu; In Bo Shim; Hyeong Rak Kim; Hae Seong Jeong - Web page: https://patentgrep.com/patent/US12217821B2 ## CPC - G11C 5/04: Supports for storage elements {, e.g. memory modules}; Mounting or fixing of storage elements on such supports - G11C 7/1087: {Data input latches} - G06F 12/0246: {in block erasable memory, e.g. flash memory} - G06F 13/1684: {using multiple buses} - G11C 7/109: {Control signal input circuits} - G11C 7/1093: {Input synchronization} - G11C 8/12: Group selection circuits, e.g. for memory block selection, chip selection, array selection - G06F 12/0653: {with centralised address assignment} - G06F 2212/7201: Logical to physical mapping or translation of blocks or pages - G06F 2212/7208: Multiple device management, e.g. distributing data over multiple flash devices - G11C: STATIC STORES (semiconductor memory devices H10B) - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract A storage device includes a memory device including a plurality of memory dies; and a memory controller for addressing a memory die among the plurality of memory dies by using an address latch enable (ALE) signal and a command latch enable (CLE) signal, which are input during predetermined N cycles, where N is a natural number, and controlling the memory device such that the memory die performs a memory operation. The memory controller may address the memory die by addressing a channel among a plurality of channels respectively connected to a plurality of package groups by using a chip enable (CE) signal. ## Claims ### Claim 1 A storage device comprising: a memory device including a plurality of memory dies and a plurality of interfaces connected to the plurality of memory dies; and a memory controller configured to: address a memory die among the plurality of memory dies by providing the memory device with an address value comprising a two bit combination of a logical value of an address latch enable (ALE) signal and a logical value of a command latch enable (CLE) signal, and control the memory device such that the memory die performs a memory operation, wherein the memory controller addresses the memory die by addressing a channel among a plurality of channels respectively connected to a plurality of package groups by using a logical value of a chip enable (CE) signal, wherein the logical value of the address latch enable (ALE) signal and the logical value of the command latch enable (CLE) signal are input to the plurality of interfaces during predetermined N cycles, where N is a natural number. ### Claim 2 (depends on 1) The storage device of claim 1, wherein each of the plurality of package groups includes a plurality of memory packages, and wherein each of the plurality of memory packages includes: a plurality of die groups each including the plurality of memory dies; and one or more interfaces among the plurality of interfaces each configured to connect corresponding die groups of the plurality of die groups to the memory controller. ### Claim 3 (depends on 2) The storage device of claim 2, wherein the memory controller addresses the memory die by addressing a memory package among the plurality of memory packages by using the logical value of the address latch enable (ALE) signal and the logical value of the command latch enable (CLE) signal during at least one cycle of the predetermined N cycles. ### Claim 4 (depends on 2) The storage device of claim 2, wherein the memory controller addresses the memory die by addressing a die group among the plurality of die groups by using the logical value of the address latch enable (ALE) signal and the logical value of the command latch enable (CLE) signal during at least one cycle. ### Claim 5 (depends on 2) The storage device of claim 2, wherein the memory controller addresses the memory die by addressing an interface among the plurality of interfaces by using the logical value of the address latch enable (ALE) signal and the logical value of the command latch enable (CLE) signal during at least one cycle. ### Claim 6 (depends on 2) The storage device of claim 2, wherein the memory controller addresses the memory die by further addressing: a memory package among the plurality of memory packages by using the logical value of the address latch enable (ALE) signal and the logical value of the command latch enable (CLE) signal during a first cycle of the predetermined N cycles, an interface among a plurality of interfaces by using the logical value of the address latch enable (ALE) signal and the logical value of the command latch enable (CLE) signal during a second cycle of the predetermined N cycles, and a die group among the plurality of die groups by using the logical value of the address latch enable (ALE) signal and the logical value of the command latch enable (CLE) signal during a third cycle of the predetermined N cycles. ### Claim 7 (depends on 1) The storage device of claim 1, wherein the memory controller addresses the memory die by using a logical value of a data (DQ) signal during the predetermined N cycles. ### Claim 8 A storage device comprising: a memory device including a plurality of memory dies and a plurality of interfaces connected to the plurality of memory dies; and a memory controller configured to provide an address latch enable (ALE) signal, a command latch enable (CLE) signal, and a chip enable (CE) signal to the plurality of interfaces during a predetermined time, wherein the plurality of interfaces address a memory die among the plurality of memory dies by using an address value comprising a two bit combination of a logical value of the address latch enable signal and a logical value of the command latch enable signal. ### Claim 9 (depends on 8) The storage device of claim 8, wherein each of a plurality of package groups includes a plurality of memory packages, and wherein each of the plurality of memory packages includes: a plurality of die groups each including the plurality of memory dies; and one or more interfaces among the plurality of interfaces each configured to connect corresponding die groups of the plurality of die groups to the memory controller. ### Claim 10 (depends on 9) The storage device of claim 9, wherein the plurality of interfaces are configured to address a memory package among the plurality of memory packages based on the logical value of the address latch enable (ALE) signal and the logical value of the command latch enable (CLE) signal, which are input during a first time in the predetermined time. ### Claim 11 (depends on 9) The storage device of claim 9, wherein the plurality of interfaces are configured to address a die group among the plurality of die groups based on the logical value of the address latch enable (ALE) signal and the logical value of the command latch enable (CLE) signal, which are input during a second time in the predetermined time. ### Claim 12 (depends on 9) The storage device of claim 9 wherein the plurality of interfaces are configured to address an interface among the plurality of interfaces based on the logical value of the address latch enable (ALE) signal and the logical value of the command latch enable (CLE) signal, which are input during a third time in the predetermined time. ### Claim 13 (depends on 9) The storage device of claim 9, wherein the plurality of interfaces address the memory die by addressing a channel among a plurality of channels respectively connected to the plurality of package groups based on a logical value of the chip enable (CE) signal and by using a data (DQ) signal input to a data line during the predetermined time. ### Claim 14 (depends on 13) The storage device of claim 13, wherein the memory controller controls the memory device to perform the memory operation by transmitting data including an address and a command to the data line such that the memory die performs the memory operation after the predetermined time. ### Claim 15 A method of operating a storage device including a plurality of memory dies and a plurality of interfaces connected to the plurality of memory dies, the method comprising: addressing a memory die among the plurality of memory dies by using an address value comprising a two bit combination of a logical value of an address latch enable (ALE) signal and a logical value of a command latch enable (CLE) signal, which are input to the plurality of interfaces during predetermined N cycles, where N is a natural number; and controlling the memory die to perform a memory operation, wherein the addressing of the memory die includes addressing a channel corresponding to the memory die among a plurality of channels respectively connected to a plurality of package groups by using a logical value of a chip enable (CE) signal. ### Claim 16 (depends on 15) The method of claim 15, wherein the addressing of the memory die further includes addressing a memory package among a plurality of memory packages by using the logical value of the address latch enable (ALE) signal and the logical value of the command latch enable (CLE) signal during at least one cycle. ### Claim 17 (depends on 15) The method of claim 15, wherein the addressing of the memory die further includes addressing a memory die group among a plurality of memory die groups by using the logical value of the address latch enable (ALE) signal and the logical value of the command latch enable (CLE) signal during at least one cycle. ### Claim 18 (depends on 15) The method of claim 15, wherein the addressing of the memory die further includes addressing an interface among the plurality of interfaces by using the logical value of the address latch enable (ALE) signal and the logical value of the command latch enable (CLE) signal, which are input during at least one cycle. ### Claim 19 (depends on 15) The method of claim 15, wherein the addressing of the memory die further includes addressing: a memory package among a plurality of memory packages by using the logical value of the address latch enable (ALE) signal and the logical value of the command latch enable (CLE) signal, which are input during a first cycle, an interface among the plurality of interfaces by using the logical value of the address latch enable (ALE) signal and the logical value of the command latch enable (CLE) signal, which are input during a second cycle, and a die group among a plurality of die groups by using the logical value of the address latch enable (ALE) signal and the logical value of the command latch enable (CLE) signal, which are input during a third cycle. ### Claim 20 (depends on 15) The method of claim 15, wherein the memory die is addressed by further using a data (DQ) signal input during the N cycles. ### Claim 21 An operating method of a memory device, the operating method comprising: selecting, in response to an address value comprising a two bit combination of a logical value of a chip enable (CE) signal from a controller, a package group of a plurality of package groups included in the memory device; selecting sequentially, in response to respective toggles of a logical value of an address latch enable (ALE) signal and a logical value of a command latch enable (CLE) signal from the controller during first to third time periods, a memory package within the selected package group, an interface within the selected memory package and a memory die group coupled to the selected interface; and performing, in response to a combination of a data (DQ) signal and the ALE and CLE signals during a fourth time period, an operation on a memory die within the selected memory die group. ### Claim 22 An operating method of a controller, the operating method comprising: selecting, by providing a memory device with an address value determined based on a combination of a logical value of a chip enable (CE) signal, a package group of a plurality of package groups included in the memory device; selecting sequentially, by providing the memory device with respective toggles of a logical value of an address latch enable (ALE) signal and a logical value of a command latch enable (CLE) signal during first to third time periods, a memory package within the selected package group, an interface within the selected memory package and a memory die group.