# US 12,217,817 B2 · Memory device and method of forming the same

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 12,217,817 B2
- Document ID: US12217817B2
- Status: Granted
- Kind: B2
- Application number: 18/356,204
- Filed: 2023-07-20
- Published: 2023-11-16
- Granted: 2025-02-04
- Earliest claimed: 2021-05-14
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Jung-Piao Chiu; Yu-Sheng Chen
- Web page: https://patentgrep.com/patent/US12217817B2

## CPC

- G11C 5/063: {Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay}
- H10B 63/10: Phase change RAM [PCRAM, PRAM] devices
- H10B 63/30: {comprising selection components having three or more electrodes, e.g. transistors}
- H10B 63/34: {of the vertical channel field-effect transistor type}
- H10B 63/845: {the switching components being connected to a common vertical conductor}
- H10W 90/00: Package configurations
- G11C 7/18: Bit line organisation; Bit line lay-out
- G11C 8/14: Word line organisation; Word line lay-out
- G11C 13/0026: {Bit-line or column circuits}
- G11C 13/0028: {Word-line or row circuits}
- G11C 13/003: {Cell access}
- G11C 2213/71: Three dimensional array
- G11C 2213/78: Array wherein the memory cells of a group share an access device, all the memory cells of the group having a common electrode and the access device being not part of a word line or a bit line driver
- G11C 2213/79: Array wherein the access device being a transistor
- H10B 63/84: {arranged in a direction perpendicular to the substrate, e.g. 3D cell arrays}
- H10N 70/011: {Manufacture or treatment of multistable switching devices}
- H10N 70/821: {Device geometry}
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H10B: ELECTRONIC MEMORY DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10N: ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR

## Abstract

A memory device includes a memory cell array. The memory cell array includes first-tier word lines extending in a first direction, second-tier word lines disposed below the first-tier word lines and extending in a second direction angularly offset from the first direction, and bit lines extending in a third direction angularly offset from the first and second directions. The bit lines are arranged between a pair of the first-tier word lines and between a pair of the second-tier word lines.

## Claims

### Claim 1

A memory device, comprising:
a memory cell array comprising:
first-tier word lines extending in a first direction;
second-tier word lines disposed below the first-tier word lines and extending in a second direction angularly offset from the first direction; and
bit lines extending in a third direction angularly offset from the first and second directions, and the bit lines being arranged between a pair of the first-tier word lines and between a pair of the second-tier word lines.

### Claim 2 (depends on 1)

The memory device of claim 1, wherein the memory cell array further comprises:
data storage layers separating the bit lines from the first-tier and second-tier word lines.

### Claim 3 (depends on 1)

The memory device of claim 1, further comprising:
transistors disposed below and electrically coupled to the memory cell array.

### Claim 4 (depends on 3)

The memory device of claim 3, further comprising:
control lines extending in the first direction and electrically connected to gate electrodes of the transistors.

### Claim 5 (depends on 3)

The memory device of claim 3, further comprising:
source lines extending in the second direction and electrically connected to source electrodes of the transistors.

### Claim 6 (depends on 3)

The memory device of claim 3, wherein each of the transistors comprises:
a source electrode; and
a drain electrode vertically between the source electrode and the memory cell array, and the drain electrode being connected to one of the bit lines.

### Claim 7 (depends on 1)

The memory device of claim 1, wherein the first, second, and third directions are substantially orthogonal to one another.

### Claim 8 (depends on 1)

The memory device of claim 1, wherein the first-tier word lines are connected together through a first common connection that extends in the second direction.

### Claim 9 (depends on 1)

The memory device of claim 1, wherein the second-tier word lines are connected together through a second common connection that extends in the first direction.

### Claim 10 (depends on 1)

The memory device of claim 1, wherein the first-tier word lines or the second-tier word lines comprises:
a first branch portion; and
a second branch portion interleaved with the first branch portion, and the first branch portion and the second branch portion are connected to different common connections.

### Claim 11 (depends on 1)

The memory device of claim 1, wherein one of the first-tier word lines comprises overlapping regions overlapping the second-tier word lines and non-overlapping regions interleaved with the overlapping regions.

### Claim 12

A memory device, comprising:
a memory cell array comprising:
first word line branches connected together through a first common connection and disposed on a first level of the memory cell array, the first word line branches extending in a first direction, and the first common connection extending in a second direction different from the first direction;
second word line branches connected together through a second common connection and disposed on a second level of the memory cell array, the second word line branches extending in the second direction, and the second common connection extending in the first direction;
bit lines extending in a third direction different from the first and second directions and passing through the first and second levels of the memory cell array.

### Claim 13 (depends on 12)

The memory device of claim 12, wherein the memory cell array further comprises:
data storage layers separating the bit lines from the first and second word line branches.

### Claim 14 (depends on 12)

The memory device of claim 12, wherein the first, second, and third directions are substantially orthogonal to one another.

### Claim 15 (depends on 12)

The memory device of claim 12, wherein the memory cell array further comprises:
third word line branches connected together through a third common connection and disposed on the first level of the memory cell array, wherein the first word line branches are interleaved with the third word line branches.

### Claim 16 (depends on 15)

The memory device of claim 15, further comprising:
transistors disposed below and electrically coupled to the memory cell array; and
control lines extending in the first direction and electrically connected to the transistors.

### Claim 17

A memory device, comprising:
a memory cell array comprising:
first word lines disposed on a first level of the memory cell array;
second word lines disposed on a second level of the memory cell array, each of the second word lines comprising overlapping regions interleaved with non-overlapping regions, wherein each of the overlapping regions overlaps one of the first word lines; and
bit lines extending through the first and second levels of the memory cell array, and the bit lines adjoining the non-overlapping region, wherein the first and second levels are stacked upon one another in a height direction of the bit lines.

### Claim 18 (depends on 17)

The memory device of claim 17, wherein the memory cell array further comprises:
data storage layers separating the bit lines from the first and second word lines.

### Claim 19 (depends on 17)

The memory device of claim 17, wherein the first and second word lines are of a comb structure.

### Claim 20 (depends on 17)

The memory device of claim 17, further comprising:
transistors disposed below and electrically coupled to the memory cell array; and
control lines disposed below the memory cell array and electrically connected to the transistors.