# US 12,217,816 B2 · Semiconductor wiring device and method

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- Number: US 12,217,816 B2
- Document ID: US12217816B2
- Status: Granted
- Kind: B2
- Application number: 17/823,173
- Filed: 2022-08-30
- Published: 2024-02-29
- Granted: 2025-02-04
- Earliest claimed: 2022-08-30
- Assignees: Micron Technology, Inc.
- Applicants: Micron Technology, Inc.
- Inventors: Hidenori Yamaguchi; Keizo Kawakita
- Web page: https://patentgrep.com/patent/US12217816B2

## CPC

- G11C 5/06: Arrangements for interconnecting storage elements electrically, e.g. by wiring
- H10B 41/00: Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- G11C 7/1006: {Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor}
- G11C 16/06: Auxiliary circuits, e.g. for writing into memory
- H10B 43/35: with cell select transistors, e.g. NAND
- H10W 20/42: Vias, e.g. via plugs
- H10B 43/00: EEPROM devices comprising charge-trapping gate insulators
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H10B: ELECTRONIC MEMORY DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

Apparatus and methods are disclosed, including transistors, semiconductor devices and systems. Example semiconductor devices and methods include a first transmission line and a second transmission line located over one another. A via is shown connecting the first transmission line and a second transmission line wherein a first side of the via and a side of the second transmission line are coplanar. A via is also shown connecting the first transmission line and a second transmission line wherein the second transmission line tapers downward from a line width to a via width.

## Claims

### Claim 1

A semiconductor device, comprising:
a first transmission line on a semiconductor substrate;
a second transmission line in a layer above the first transmission line, the second transmission line having a line width; and
a via coupled between the first transmission line and the second transmission line, wherein the via has a via width smaller than the line width;
wherein the second transmission line tapers downward from the line width to the via width.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein the second transmission line and the via are integral.

### Claim 3 (depends on 1)

The semiconductor device of claim 1, wherein the second transmission line and the via include copper.

### Claim 4 (depends on 1)

The semiconductor device of claim 1, wherein the first transmission line is oriented orthogonal to the second transmission line.

### Claim 5 (depends on 1)

The semiconductor device of claim 1, wherein the first transmission line is oriented parallel to the second transmission line.

### Claim 6 (depends on 1)

The semiconductor device of claim 1, wherein a side of the via and a side of the second transmission line are coplanar.

### Claim 7

A semiconductor device, comprising:
a first transmission line on a semiconductor substrate;
a second transmission line in a layer above the first transmission line, the second transmission line having a line width; and
a via coupled between the first transmission line and the second transmission line;
wherein a first side of the via and a side of the second transmission line are coplanar.

### Claim 8 (depends on 7)

The semiconductor device of claim 7, wherein the via includes a second straight side opposite the first side of the via.

### Claim 9 (depends on 7)

The semiconductor device of claim 7, wherein the via is substantially rectangular.

### Claim 10 (depends on 7)

The semiconductor device of claim 7, wherein the via has a width equal to the line width.

### Claim 11 (depends on 7)

The semiconductor device of claim 7, wherein the first line and second line are orthogonal and define an intersection, and further including a second via at the intersection.

### Claim 12 (depends on 7)

The semiconductor device of claim 7, wherein the first line and second line are parallel.

### Claim 13

A method, comprising:
forming a first transmission line on a semiconductor substrate;
forming a dielectric over the first transmission line;
using a trench mask to lithographically form a trench in the dielectric for a second transmission line above the first transmission line;
using a via mask to lithographically form a via opening in the dielectric, wherein a via mask footprint and a trench mask footprint overlap in an intersection region smaller than either the via mask or the trench mask, and wherein the via opening is dimensioned by the intersection region; and
filling the trench and via opening in a single conductor deposition operation.

### Claim 14 (depends on 13)

The method of claim 13, wherein the trench is formed before the via opening.

### Claim 15 (depends on 13)

The method of claim 13, further including etching within the trench and the via opening concurrently, forming a downward taper from one side of the trench to the via opening.

### Claim 16 (depends on 13)

The method of claim 13, wherein using a via mask to lithographically form a via opening includes the intersection region spanning a width of the trench mask.

### Claim 17 (depends on 13)

The method of claim 13, wherein using a via mask to lithographically form a via opening includes using a single via mask to form two or more adjacent intersection regions to form two or more adjacent via openings.