# US 12,217,813 B2 · Apparatuses and methods for tracking word line accesses

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- Number: US 12,217,813 B2
- Document ID: US12217813B2
- Status: Granted
- Kind: B2
- Application number: 17/822,033
- Filed: 2022-08-24
- Published: 2022-12-29
- Granted: 2025-02-04
- Earliest claimed: 2020-11-23
- Applicants: Lodestar Licensing Group LLC
- Inventors: Dong Pan
- Web page: https://patentgrep.com/patent/US12217813B2

## CPC

- G11C 8/08: Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
- G11C 29/42: using error correcting codes [ECC] or parity check
- G11C 7/065: {Differential amplifiers of latching type}
- G11C 7/24: Memory cell safety or protection circuits, e.g. arrangements for preventing inadvertent reading or writing; Status cells; Test cells
- G11C 11/40611: {External triggering or timing of internal or partially internal refresh operations, e.g. auto-refresh or CAS-before-RAS triggered refresh}
- G11C 11/4078: Safety or protection circuits, e.g. for preventing inadvertent or unauthorised reading or writing; Status cells; Test cells (protection of memory contents during checking or testing G11C29/52)
- G11C 11/4087: {Address decoders, e.g. bit - or word line decoders; Multiple line decoders}
- G11C 29/20: using counters or linear-feedback shift registers [LFSR]
- G11C 29/44: Indication or identification of errors, e.g. for repair
- G11C 2029/0411: {Online error correction}
- G11C 2029/1202: {Word line control}
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

Counters may be provided for individual word lines of a memory for tracking word line accesses. In some examples, multiple counters may be provided for individual word lines. In some examples, the counters may be included on the word lines. The counters may be incremented responsive to word line accesses in some examples. In some examples, the counters may be incremented responsive for a time period for which a word line is held open. In some examples, the counters may be incremented responsive to both word line accesses and time periods for which the word line is held open. In some examples, count values for the counters may be written back to the counters after incrementing. In some examples, the count values may be written back prior to receiving a precharge command.

## Claims

### Claim 1

An apparatus comprising:
a memory array comprising a plurality of word lines, wherein each of the plurality of word lines comprises a plurality of count value memory cells configured to store a plurality of values each representing a number of activations of a corresponding one of the plurality of word lines;
a count control circuit configured to receive a value of the plurality of values from the plurality of count value memory cells of a word line of the plurality of word lines when the word line is activated, compare the value to a threshold value and activate a trigger signal when the value is equal to or greater than the threshold value; and
a refresh control circuit configured to latch a current row address and perform a targeted refresh operation when the active trigger signal is received.

### Claim 2 (depends on 1)

The apparatus of claim 1, wherein the refresh control circuit is further configured to activate a busy signal provided to an external pin when performing the targeted refresh operation.

### Claim 3 (depends on 2)

The apparatus of claim 2, wherein the refresh control circuit is configured to perform the targeted refresh operation outside a scheduled refresh mode.

### Claim 4 (depends on 1)

The apparatus of claim 1, wherein the count control circuit is further configured to update a value of the plurality of values and provide the updated value to the plurality of count value memory cells of the word line after a precharge command is received.

### Claim 5 (depends on 1)

The apparatus of claim 1, wherein a value of the plurality of values is further associated with an amount of time of activation of the corresponding one of the plurality of word lines.

### Claim 6 (depends on 1)

The apparatus of claim 1, wherein the plurality of count value memory cells are further configured to store error correction code information associated with the plurality of values.

### Claim 7

A method comprising:
storing a plurality of values each representing a different one of a number of activations of a word line in a plurality of count value memory cells of the word line;
comparing a value of the plurality of values to a threshold value with a count control circuit; and
activating a trigger signal when the value is equal to or greater than the threshold value; and
updating the value when the value is below the threshold value.

### Claim 8 (depends on 7)

The method of claim 7, further comprising:
activating the word line; and
receiving the value of the plurality of values when the word line is activated at the count control circuit.

### Claim 9 (depends on 7)

The method of claim 7, further comprising latching a current row address when the trigger signal is received.

### Claim 10 (depends on 9)

The method of claim 9, further comprising performing a targeted refresh operation.

### Claim 11 (depends on 10)

The method of claim 10, wherein the targeted refresh operation is performed on the word line at an address based on the current row address latched.

### Claim 12 (depends on 10)

The method of claim 10, further comprising activating a busy signal provided to an external pin.

### Claim 13 (depends on 7)

The method of claim 7, further comprising:
determining a correct value for the value, at least in part, on a comparison of the plurality of values to one another; and
providing the correct value to the plurality of count value memory cells.

### Claim 14 (depends on 13)

The method of claim 13, further comprising:
comparing the correct value to the threshold value;
activating the trigger signal when the correct value is equal to or greater than the threshold value; and
updating the correct value when the correct value is below the threshold value.

### Claim 15

An apparatus comprising:
a memory array comprising a word line comprising:
a plurality of memory cells; and
a plurality of count value memory cells configured to store a plurality of values each representing a number of activations of the word line, wherein the plurality of count value memory cells are included in the plurality of memory cells.

### Claim 16 (depends on 15)

The apparatus of claim 15, further comprising a count control circuit configured to receive at least one value of the plurality of values, compare the at least one value to a threshold value, and activate a trigger signal when the value is equal to or greater than the threshold value.

### Claim 17 (depends on 16)

The apparatus of claim 16, further comprising a refresh control circuit configured to latch a current row address and perform a targeted refresh operation when the active trigger signal is received.

### Claim 18 (depends on 17)

The apparatus of claim 17, further comprising an external pin, wherein the refresh control circuit is further configured to activate a busy signal provided to the external pin when performing the targeted refresh operation.

### Claim 19 (depends on 16)

The apparatus of claim 16, wherein the count control circuit is further configured to compare the plurality of values to one another, determine a correct value, and update the correct value to generate the at least one updated value.

### Claim 20 (depends on 15)

The apparatus of claim 15, further comprising a timer to count how long the word line remains at an activation voltage, an activation signal is active, or a combination thereof, wherein the plurality of values further represent an amount of time of activation of the word line.