# US 12,217,810 B2 · Memory readout circuit and method > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,217,810 B2 - Document ID: US12217810B2 - Status: Granted - Kind: B2 - Application number: 18/601,100 - Filed: 2024-03-11 - Published: 2024-06-27 - Granted: 2025-02-04 - Earliest claimed: 2020-03-31 - Assignees: Taiwan Semiconductor Manufacturing Company, Ltd. - Applicants: Taiwan Semiconductor Manufacturing Company, Ltd. - Inventors: Chih-Min Liu - Web page: https://patentgrep.com/patent/US12217810B2 ## CPC - G11C 11/005: {comprising combined but independently operative RAM-ROM, RAM-PROM, RAM-EPROM cells} - G11C 17/18: Auxiliary circuits, e.g. for writing into memory - G11C 11/1655: {Bit-line or column circuits} - G11C 11/1673: {Reading or sensing circuits or methods} - G11C 11/5607: {using magnetic storage elements} - G11C 11/5692: {read-only digital stores using storage elements with more than two stable states} - G11C 13/0026: {Bit-line or column circuits} - G11C 13/004: {Reading or sensing circuits or methods} - G11C 17/16: using electrically-fusible links - G11C 11/161: {details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell} - G11C 11/1659: {Cell access} - G11C 2013/0054: {Read is performed on a reference element, e.g. cell, and the reference sensed value is used to compare the sensed value of the selected cell} - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract A circuit includes a plurality of anti-fuse cells coupled to a first selection circuit, a plurality of magnetic random-access memory (MRAM) cells coupled to a second selection circuit, an amplifier including a first input terminal coupled to each of the first and second selection circuits, an analog-to-digital converter (ADC) including input terminals coupled to output terminals of the amplifier, and a comparator including a first input port coupled to an output port of the ADC. The amplifier, ADC, and comparator are configured to output data bits from the comparator responsive to current levels received from the first selection circuit at the first input terminal of the amplifier and first voltage levels received from the second selection circuit at the first input terminal of the amplifier. ## Claims ### Claim 1 A circuit comprising: a plurality of anti-fuse cells coupled to a first selection circuit; a plurality of magnetic random-access memory (MRAM) cells coupled to a second selection circuit; an amplifier comprising a first input terminal coupled to each of the first and second selection circuits; an analog-to-digital converter (ADC) comprising input terminals coupled to output terminals of the amplifier; and a comparator comprising a first input port coupled to an output port of the ADC, wherein the amplifier, ADC, and comparator are configured to output data bits from the comparator responsive to: current levels received from the first selection circuit at the first input terminal of the amplifier, and first voltage levels received from the second selection circuit at the first input terminal of the amplifier. ### Claim 2 (depends on 1) The circuit of claim 1, wherein the plurality of MRAM cells is further coupled to a third selection circuit, the amplifier comprises a second input terminal coupled to the third selection circuit, and the amplifier, ADC, and comparator are configured to output the data bits from the comparator further responsive to second voltage levels received from the third selection circuit. ### Claim 3 (depends on 2) The circuit of claim 2, further comprising: a first switching device coupled between the third selection circuit and a power supply node; and a second switching device coupled between the third selection circuit and a power supply reference node. ### Claim 4 (depends on 3) The circuit of claim 3, further comprising: a third switching device and a first current source coupled in series between the first selection circuit and the power supply node; and a fourth switching device and a second current source coupled in series between the first selection circuit and the power supply reference node. ### Claim 5 (depends on 1) The circuit of claim 1, wherein the plurality of anti-fuse cells is configured to receive first and second signals having first and second voltage levels with respect to a reference voltage level, the amplifier comprises a second input terminal, and the circuit further comprises a first switching device coupled between the second input terminal of the amplifier and a voltage node configured to carry the reference voltage level. ### Claim 6 (depends on 5) The circuit of claim 5, further comprising: a second switching device coupled between the first and second input terminals of the amplifier. ### Claim 7 (depends on 1) The circuit of claim 1, wherein the amplifier, ADC, and comparator are configured to output the data bits responsive to the current levels based on the amplifier comprising an operational amplifier configured as an integrator, and the amplifier, ADC, and comparator are configured to output the data bits responsive to the first voltage levels based on the operational amplifier configured as a differential amplifier. ### Claim 8 (depends on 7) The circuit of claim 7, wherein the amplifier further comprises: a second input terminal; a first capacitive device coupled between the first input terminal and an inverting input terminal of the operational amplifier; a second capacitive device coupled between the second input terminal and a non-inverting input terminal of the operational amplifier; a third capacitive device coupled between the inverting input terminal and a first output terminal of the output terminals of the operational amplifier; and a fourth capacitive device coupled between the non-inverting input terminal and a second output terminal of the output terminals of the operational amplifier. ### Claim 9 (depends on 8) The circuit of claim 8, wherein each of the third and fourth capacitive devices has a variable capacitance level. ### Claim 10 A circuit comprising: a plurality of anti-fuse cells coupled to a first selection circuit; a plurality of magnetic random-access memory (MRAM) cells coupled to a second selection circuit; an amplifier comprising a first input terminal coupled to each of the first and second selection circuits; an analog-to-digital converter (ADC) comprising input terminals coupled to output terminals of the amplifier; and a comparator comprising: a first input port coupled to an output port of the ADC; and a second input port configured to receive a plurality of threshold levels, wherein the amplifier, ADC, and comparator are configured to output data bits from the comparator responsive to the plurality of threshold levels and each of: current levels received from the first selection circuit at the first input terminal of the amplifier, and voltage levels received from the second selection circuit at the first input terminal of the amplifier. ### Claim 11 (depends on 10) The circuit of claim 10, wherein the amplifier, ADC, and comparator are configured to output the data bits responsive to the current levels based on the amplifier having an integrator configuration, and the comparator receiving a first threshold level of the plurality of threshold levels, and the amplifier, ADC, and comparator are configured to output the data bits responsive to the first voltage levels based on the amplifier having a differential amplifier configuration, and the comparator receiving a second threshold level of the plurality of threshold levels. ### Claim 12 (depends on 10) The circuit of claim 10, wherein the second input port of the comparator is coupled to the plurality of anti-fuse cells, and the plurality of threshold levels is stored in the plurality of anti-fuse cells. ### Claim 13 (depends on 10) The circuit of claim 10, wherein the plurality of MRAM cells is further coupled to a third selection circuit, the amplifier comprises a second input terminal coupled to the third selection circuit, and the amplifier, ADC, and comparator are configured to output the data bits from the comparator further responsive to second voltage levels received from the third selection circuit. ### Claim 14 (depends on 13) The circuit of claim 13, further comprising: a first switching device coupled between the first selection circuit and a first current source; a second switching device coupled between the first selection circuit and a second current source; a third switching device coupled between the third selection circuit and a power supply node; and a fourth switching device coupled between the third selection circuit and a power supply reference node. ### Claim 15 (depends on 10) The circuit of claim 10, wherein the plurality of anti-fuse cells is configured to receive first and second signals, the amplifier comprises a second input terminal and a first switching device coupled between the first and second input terminals, and the circuit further comprises a second switching device coupled between the second input terminal of the amplifier and a voltage node configured to carry a virtual ground voltage level. ### Claim 16 A method of operating a memory circuit, the method comprising: performing first read operations comprising: accessing a plurality of anti-fuse cells with a first selection circuit; receiving current levels from the first selection circuit at a first input terminal of an amplifier; and using the amplifier, an analog-to-digital converter (ADC) coupled to the amplifier, and a comparator coupled to the ADC to output first data bits in response to the current levels; and performing second read operations comprising: accessing a plurality of magnetic random-access memory (MRAM) cells with a second selection circuit; receiving first voltage levels from the second selection circuit at the first input terminal of the amplifier; and using the amplifier, ADC, and comparator to output second data bits in response to the first voltage levels. ### Claim 17 (depends on 16) The method of claim 16, wherein the using the amplifier, ADC, and comparator to output the first data bits comprises using the comparator to compare first ADC outputs to a first threshold level, and the using the amplifier, ADC, and comparator to output the second data bits comprises using the comparator to compare second ADC outputs to a second threshold level. ### Claim 18 (depends on 17) The method of claim 17, wherein the using the comparator to compare the first ADC outputs to the first threshold level comprises receiving the first threshold level from the plurality of anti-fuse cells, and the using the comparator to compare the second ADC outputs to the second threshold level comprises receiving the second threshold level from the plurality of anti-fuse cells. ### Claim 19 (depends on 16) The method of claim 16, wherein the performing the second read operations further comprises: accessing the plurality of MRAM cells with a third selection circuit; receiving second voltage levels from the third selection circuit at a second input terminal of the amplifier; and using the amplifier, ADC, and comparator to output the second data bits further in response to the second voltage levels. ### Claim 20 (depends on 19) The method of claim 19, wherein the using the amplifier, ADC, and comparator to output the first data bits comprises using the amplifier configured as an integrator, and the using the amplifier, ADC, and comparator to output the second data bits comprises using the amplifier configured as a differential amplifier.