# US 12,217,809 B2 · One-time programmable bitcell for frontside and backside power interconnect

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- Number: US 12,217,809 B2
- Document ID: US12217809B2
- Status: Granted
- Kind: B2
- Application number: 18/071,321
- Filed: 2022-11-29
- Published: 2023-06-15
- Granted: 2025-02-04
- Earliest claimed: 2021-12-15
- Assignees: Synopsys, Inc.
- Applicants: Synopsys, Inc.
- Inventors: Andrew Edward Horch
- Web page: https://patentgrep.com/patent/US12217809B2

## CPC

- G11C 17/16: using electrically-fusible links
- G11C 17/18: Auxiliary circuits, e.g. for writing into memory
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

A bitcell of a one-time programmable memory includes: a write-once programmable circuit element and a node connected in series between a word line and a power rail; a select read device connected between the node and a bitline, the select read device having a gate electrode connected to a first signal line extending parallel to the word line; and a select write device connected between the word line and the power rail and in series with the write-once programmable circuit element and the node, the select write device having a gate electrode connected to a second signal line extending parallel to the bitline.

## Claims

### Claim 1

A bitcell of a one-time programmable memory comprising:
a write-once programmable circuit element and a node connected in series between a word line and a power rail;
a select read device connected between the node and a bitline, the select read device having a gate electrode connected to a first signal line extending substantially parallel to the word line; and
a select write device connected between the word line and the power rail and in series with the write-once programmable circuit element and the node, the select write device having a gate electrode connected to a second signal line extending substantially parallel to the bitline.

### Claim 2 (depends on 1)

The bitcell of claim 1, wherein the write-once programmable circuit element is a positive metal oxide semiconductor (PMOS) anti-fuse.

### Claim 3 (depends on 1)

The bitcell of claim 1, wherein the select write device comprises a cascode negative metal oxide semiconductor (NMOS) device.

### Claim 4 (depends on 3)

The bitcell of claim 3, wherein the cascode NMOS device comprises:
a first NMOS transistor having the gate electrode connected to the second signal line; and
a second NMOS transistor connected in series with the first NMOS transistor and having a gate electrode connected to a third signal line extending substantially perpendicular to the second signal line.

### Claim 5 (depends on 1)

The bitcell of claim 1, wherein the select read device comprises a cascode NMOS device comprising:
a first NMOS transistor having the gate electrode connected to the first signal line; and
a second NMOS transistor connected in series with the first NMOS transistor and having a gate electrode connected to a third signal line extending substantially parallel to the first signal line.

### Claim 6 (depends on 1)

The bitcell of claim 1, wherein the bitline has lower capacitance than the word line, and wherein the word line has lower resistance than the bitline.

### Claim 7 (depends on 1)

The bitcell of claim 1, wherein the one-time programmable memory further comprises a second one-time programmable bitcell comprising:
a second write-once programmable circuit element and a second node connected in series between the word line and the power rail;
a second select read device connected between the second node and a second bitline extending parallel to the bitline, the second select read device having a gate electrode connected to the first signal line; and
a second select write device connected between the word line and the second node and in series with the second write-once programmable circuit element and the second node, the second select write device having a gate electrode connected to a third signal line extending substantially parallel to the bitline.

### Claim 8 (depends on 7)

The bitcell of claim 7, wherein the select write device comprises a cascode NMOS device comprising:
a first NMOS transistor having the gate electrode connected to the second signal line; and
a second NMOS transistor connected in series with the first NMOS transistor and having a gate electrode connected to a fourth signal line extending substantially perpendicular to the second signal line, and
wherein the second select write device comprises a cascode NMOS device comprising:
a first NMOS transistor having the gate electrode connected to the third signal line; and
a second NMOS transistor connected in series with the first NMOS transistor and having a gate electrode connected to the fourth signal line.