# US 12,217,808 B2 · Methods and apparatus for NAND flash memory > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,217,808 B2 - Document ID: US12217808B2 - Status: Granted - Kind: B2 - Application number: 17/816,720 - Filed: 2022-08-01 - Published: 2023-01-26 - Granted: 2025-02-04 - Earliest claimed: 2018-11-18 - Assignees: NEO Semiconductor, Inc. - Applicants: NEO Semiconductor, Inc. - Inventors: Fu-Chang Hsu - Web page: https://patentgrep.com/patent/US12217808B2 ## CPC - G11C 16/0483: {comprising cells having several storage transistors connected in series} - G11C 16/3459: {Circuits or methods to verify correct programming of nonvolatile memory cells} - G11C 11/5628: {Programming or writing circuits; Data input circuits} - G11C 11/5642: {Sensing or reading circuits; Data output circuits} - G11C 16/10: Programming or data input circuits - G11C 16/12: Programming voltage switching circuits - G11C 16/24: Bit-line control circuits - G11C 16/26: Sensing or reading circuits; Data output circuits - G11C 16/30: Power supply circuits - G11C 16/3427: {Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written} - G11C 16/32: Timing circuits - G11C 2211/5641: Multilevel memory having cells with different number of storage levels - G11C 2211/5642: Multilevel memory with buffers, latches, registers at input or output - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract Methods and apparatus for NAND flash memory are disclosed. In an embodiment, a method is provided for programming a memory device having a plurality of memory chips that comprise multiple-level-cells. The method includes loading first data in a first chip, programming the first data into selected cells of the first chip using a single-level-cell (SLC) programming mode, and reprogramming the first data stored in the selected cells of the first chip to other cells of the first chip using a multiple-level-cell programming mode. The method also includes repeating the operations of loading, programming, and reprogramming for the remaining chips. The loading operations for the remaining chips begin at the completion of the loading operation for the first chip and occur in a non-overlapping sequential manner, and the loading operations for the remaining chips are performed in parallel with the programming and reprogramming operations of the first chip. ## Claims ### Claim 1 A method for programming a memory device having a plurality of memory chips wherein each chip has multiple-level-cells, the method comprising: loading first data in a first chip; programming the first data into selected cells of the first chip using a single-level-cell (SLC) programming mode; reprogramming the first data stored in the selected cells of the first chip to other cells of the first chip using a multiple-level-cell programming mode; repeating the operations of loading, programming, and reprogramming for the remaining chips; wherein the loading operations for the remaining chips begin at the completion of the loading operation for the first chip and occur in a non-overlapping sequential manner; and wherein the loading operations for the remaining chips are performed in parallel with the programming and reprogramming operations of the first chip. ### Claim 2 (depends on 1) The method of claim 1, wherein the multiple-level-cells are one type of multiple-level-cell selected from a set comprising multi-level cell (MLC), triple-level cell (TLC), quad-level cell (QLC), penta-level cell (PLC), and hex-level cell (HLC). ### Claim 3 (depends on 1) The method of claim 1, wherein the multiple-level-cells of the first chip form a plurality of planes, and wherein the selected cells are in a first group of planes and the other cells are in a second group of planes. ### Claim 4 (depends on 3) The method of claim 3, wherein a number of planes to achieve a selected I/O bandwidth is determined from the expression: (Plane number>I/O bandwidth×(One chip loading time+SLC Program time+TLC Program time)/Chip Number/Bit line number per plane). ### Claim 5 (depends on 1) The method of claim 1, the method operates to program the memory device without idle time between loading operations. ### Claim 6 A method for programming a memory device having a plurality of memory chips wherein each chip has multiple-level-cells, the method comprising: loading data into a first chip; programming the data loaded into the first chip into cells of the first chip; and after the operation of loading the data into the first chip completes, loading additional data into the remaining chips of the memory device in a non-overlapping chip-by-chip sequence so that all the additional data is loaded into the remaining chips in parallel with the programming of the first chip; wherein the operation of programming comprises: programming the first data into selected cells of the first chip using a single-level-cell (SLC) programming mode; and reprogramming the first data stored in the selected cells of the first chip to other cells of the first chip using a multiple-level-cell programming mode. ### Claim 7 (depends on 6) The method of claim 6, wherein the multiple-level-cells are one type of multiple-level-cell selected from a set comprising multi-level cell (MLC), triple-level cell (TLC), quad-level cell (QLC), penta-level cell (PLC), and hex-level cell (HLC). ### Claim 8 (depends on 6) The method of claim 6, wherein the multiple-level-cells of the first chip form a plurality of planes, and wherein the selected cells are in a first group of planes and the other cells are in a second group of planes. ### Claim 9 (depends on 8) The method of claim 8, wherein a number of planes to achieve a selected I/O bandwidth is determined from the expression: (Plane number>I/O bandwidth×(One chip loading time+SLC Program time+TLC Program time)/Chip Number/Bit line number per plane). ### Claim 10 (depends on 6) The method of claim 6, the method operates to program the memory device without idle time between loading operations. ### Claim 11 (depends on 6) The method of claim 6, wherein the loading operations for the remaining chips are completed before the completion of the operation of programming the data loaded into the first chip.