# US 12,217,806 B2 · Techniques for threshold voltage scans > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,217,806 B2 - Document ID: US12217806B2 - Status: Granted - Kind: B2 - Application number: 17/871,234 - Filed: 2022-07-22 - Published: 2024-01-25 - Granted: 2025-02-04 - Earliest claimed: 2022-07-22 - Assignees: Micron Technology, Inc. - Applicants: Micron Technology, Inc. - Inventors: Aniello Palomba; Ciro Feliciano; Antonio Imperiale - Web page: https://patentgrep.com/patent/US12217806B2 ## CPC - G11C 16/34: Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention - G11C 16/26: Sensing or reading circuits; Data output circuits - G11C 16/0483: {comprising cells having several storage transistors connected in series} - G11C 2029/0409: {Online test} - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract Methods, systems, and devices for threshold voltage scans are described. A memory device may receive a configuration for scanning a memory array during a scanning procedure. The memory device may read, during the scanning procedure, one or more memory cells of the memory array using a first voltage value that is indicated by the configuration. The memory device may store, during the scanning procedure, a first value in a first counter in response to reading the one or more memory cells of the memory array. The memory device may determine whether to terminate the scanning procedure in response to one or both of determining that the first quantity of memory cells satisfies a threshold quantity of memory cells or determining that the first voltage value satisfies a threshold voltage value to be scanned. ## Claims ### Claim 1 A memory system, comprising: one or more memory devices; and one or more controllers coupled with the one or more memory devices and configured to cause the memory system to: receive a configuration for scanning a memory array during a scanning procedure; read, during the scanning procedure, one or more memory cells of the memory array using a first voltage value of a plurality of incremental voltage values that are in accordance with the configuration; store, during the scanning procedure, a first value in a first counter in response to reading the one or more memory cells of the memory array, the first value corresponding to a first quantity of memory cells of the memory array; and determine whether to terminate the scanning procedure in accordance with one or both of whether the first quantity of memory cells satisfies a threshold quantity of memory cells or whether the first voltage value satisfies a threshold voltage value associated with the one or more memory cells. ### Claim 2 (depends on 1) The memory system of claim 1, wherein the one or more controllers are further configured to cause the memory system to: terminate the scanning procedure in response to determining that the first quantity of memory cells satisfies the threshold quantity of memory cells or the first voltage value satisfies the threshold voltage value, or both. ### Claim 3 (depends on 1) The memory system of claim 1, wherein the one or more controllers are further configured to cause the memory system to: refrain from terminating the scanning procedure in response to determining that the first quantity of memory cells fails to satisfy the threshold quantity of memory cells or the first voltage value fails to satisfy the threshold voltage value, or both. ### Claim 4 (depends on 3) The memory system of claim 3, wherein the one or more controllers are further configured to cause the memory system to: determine whether the first value stored in the first counter is equal to a first value stored in a second counter in response to refraining from terminating the scanning procedure, wherein the second counter is configured to store values previously stored in the first counter. ### Claim 5 (depends on 4) The memory system of claim 4, wherein the one or more controllers are further configured to cause the memory system to: determine a voltage step size value in response to determining that the first value stored in the first counter is equal to the first value stored in the second counter; and determine a first voltage offset value in response to determining the voltage step size value. ### Claim 6 (depends on 5) The memory system of claim 5, wherein the one or more controllers are further configured to cause the memory system to: determine a second voltage value of the plurality of incremental voltage values in accordance with the first voltage value and the first voltage offset value; and store, in the second counter, the first value stored in the first counter. ### Claim 7 (depends on 6) The memory system of claim 6, wherein the one or more controllers are further configured to cause the memory system to: read the one or more memory cells of the memory array using the second voltage value during the scanning procedure; store a second value in the first counter in response to reading the one or more memory cells of the memory array, the second value corresponding to a second quantity of memory cells of the memory array; and determine whether to terminate the scanning procedure in accordance with whether the second quantity of memory cells satisfies the threshold quantity of memory cells or whether the second voltage value satisfies the threshold voltage value, or both. ### Claim 8 (depends on 4) The memory system of claim 4, wherein the one or more controllers are further configured to cause the memory system to: determine whether a second voltage offset value is equal to a multiple of a voltage step size value. ### Claim 9 (depends on 8) The memory system of claim 8, wherein the one or more controllers are further configured to cause the memory system to: determine a second voltage value of the plurality of incremental voltage values in accordance with the first voltage value and a first voltage offset value, wherein the first voltage offset value is in accordance with the voltage step size value and determining the second voltage value is in response to determining that the second voltage offset value is different from the multiple of the voltage step size value; and store, in the second counter, the first value stored in the first counter. ### Claim 10 (depends on 8) The memory system of claim 8, wherein the one or more controllers are further configured to cause the memory system to: determine a third voltage offset value in response to determining that the second voltage offset value is equal to the multiple of the voltage step size value, wherein the third voltage offset value is equal to the voltage step size value; determine a second voltage value of the plurality of incremental voltage values in accordance with a difference between the second voltage offset value and the first voltage value; and store, in the second counter, the first value stored in the first counter. ### Claim 11 (depends on 10) The memory system of claim 10, wherein the one or more controllers are further configured to cause the memory system to: read the one or more memory cells of the memory array using the second voltage value during the scanning procedure; store a second value in the first counter in response to reading the one or more memory cells of the memory array, the second value corresponding to a second quantity of memory cells of the memory array; and determine whether to terminate the scanning procedure in accordance with whether the second quantity of memory cells satisfies the threshold quantity of memory cells or whether the second voltage value satisfies the threshold voltage value, or both. ### Claim 12 A non-transitory computer-readable medium storing code comprising instructions which, when executed by one or more processors of an electronic device, cause the electronic device to: receive a configuration for scanning a memory array during a scanning procedure; read, during the scanning procedure, one or more memory cells of the memory array using a first voltage value of a plurality of incremental voltage values that are in accordance with the configuration; store, during the scanning procedure, a first value in a first counter in response to reading the one or more memory cells of the memory array, the first value corresponding to a first quantity of memory cells of the memory array; and determine whether to terminate the scanning procedure in accordance with one or both of whether the first quantity of memory cells satisfies a threshold quantity of memory cells or whether the first voltage value satisfies a threshold voltage value associated with the one or more memory cells. ### Claim 13 (depends on 12) The non-transitory computer-readable medium of claim 12, wherein the instructions, when executed by the one or more processors of the electronic device, further cause the electronic device to: terminate the scanning procedure in response to determining that the first quantity of memory cells satisfies the threshold quantity of memory cells or the first voltage value satisfies the threshold voltage value, or both. ### Claim 14 (depends on 12) The non-transitory computer-readable medium of claim 12, wherein the instructions, when executed by the one or more processors of the electronic device, further cause the electronic device to: refrain from terminating the scanning procedure in response to determining that the first quantity of memory cells fails to satisfy the threshold quantity of memory cells or the first voltage value fails to satisfy the threshold voltage value, or both. ### Claim 15 (depends on 14) The non-transitory computer-readable medium of claim 14, wherein the instructions, when executed by the one or more processors of the electronic device, further cause the electronic device to: determine whether the first value stored in the first counter is equal to a first value stored in a second counter in response to refraining from terminating the scanning procedure, wherein the second counter is configured to store values previously stored in the first counter. ### Claim 16 (depends on 15) The non-transitory computer-readable medium of claim 15, wherein the instructions, when executed by the one or more processors of the electronic device, further cause the electronic device to: determine a voltage step size value in response to determining that the first value stored in the first counter is equal to the first value stored in the second counter; and determine a first voltage offset value in response to determining the voltage step size value. ### Claim 17 (depends on 16) The non-transitory computer-readable medium of claim 16, wherein the instructions, when executed by the one or more processors of the electronic device, further cause the electronic device to: determine a second voltage value of the plurality of incremental voltage values in accordance with the first voltage value and the first voltage offset value; and store, in the second counter, the first value stored in the first counter. ### Claim 18 (depends on 17) The non-transitory computer-readable medium of claim 17, wherein the instructions, when executed by the one or more processors of the electronic device, further cause the electronic device to: read the one or more memory cells of the memory array using the second voltage value during the scanning procedure; store a second value in the first counter in response to reading the one or more memory cells of the memory array, the second value corresponding to a second quantity of memory cells of the memory array; and determine whether to terminate the scanning procedure in accordance with whether the second quantity of memory cells satisfies the threshold quantity of memory cells or whether the second voltage value satisfies the threshold voltage value, or both. ### Claim 19 (depends on 15) The non-transitory computer-readable medium of claim 15, wherein the instructions, when executed by the one or more processors of the electronic device, further cause the electronic device to: determine whether a second voltage offset value is equal to a multiple of a voltage step size value. ### Claim 20 A method by a memory system, comprising: receiving a configuration for scanning a memory array during a scanning procedure; reading, during the scanning procedure, one or more memory cells of the memory array using a first voltage value of a plurality of incremental voltage values that are in accordance with the configuration; storing, during the scanning procedure, a first value in a first counter in response to reading the one or more memory cells of the memory array, the first value corresponding to a first quantity of memory cells of the memory array; and determining whether to terminate the scanning procedure in accordance with one or both of whether the first quantity of memory cells satisfies a threshold quantity of memory cells or whether the first voltage value satisfies a threshold voltage value associated with the one or more memory cells.