# US 12,217,802 B2 · Non-volatile memory device, storage device including the same, and operating method thereof > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,217,802 B2 - Document ID: US12217802B2 - Status: Granted - Kind: B2 - Application number: 17/648,311 - Filed: 2022-01-19 - Published: 2022-12-29 - Granted: 2025-02-04 - Earliest claimed: 2021-06-28 - Assignees: Samsung Electronics Co., Ltd. - Applicants: Samsung Electronics Co., Ltd. - Inventors: Jooyong Park; Sangwon Park; Dongjin Shin; Suchang Jeon; Seungyong Choi - Web page: https://patentgrep.com/patent/US12217802B2 ## CPC - G11C 16/26: Sensing or reading circuits; Data output circuits - G11C 16/0483: {comprising cells having several storage transistors connected in series} - G11C 16/08: Address circuits; Decoders; Word-line control circuits - G11C 16/14: Circuits for erasing electrically, e.g. erase voltage switching circuits - G11C 16/20: Initialising; Data preset; Chip identification - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract A non-volatile memory device includes a meta area having a first region storing first initial data, and second regions storing second initial data, different from each other; a user area configured to store user data; an initialization register configured to store the first initial data or update the second initial data in whole or in part; and control logic configured to perform a read operation, a program operation, or an erase operation using the initial data stored in the initialization register. ## Claims ### Claim 1 A non-volatile memory device comprising: a meta area having a first region storing first initial data, and second regions storing second initial data, different from each other; a user area configured to store user data; an initialization register configured to store the first initial data or the second initial data, and to update the second initial data in whole or in part; and control logic configured to receive a command latch enable signal, an address latch enable signal, a chip enable signal, a write enable signal, a read enable signal, and a data strobe signal through control pins and latch a command or an address at an edge of the write enable signal according to the chip enable signal and the address latch enable signal, to perform a read operation, a program operation, or an erase operation using the initial data stored in the initialization register, wherein one of the first initial data or the second initial data comprises at least one performance parameter related to an operation time of the non-volatile memory device, wherein the other of the first initial data or the second initial data comprises at least one reliability parameter related to at least one of retention, endurance, voltage or verification of the non-volatile memory device, wherein one of the first initial data or the second initial data is provided in common, and the other of the first initial data or the second initial data is selectable by a user. ### Claim 2 (depends on 1) The non-volatile memory device of claim 1, wherein, during a power-up operation, an initial data read command is received externally, wherein the at least one performance parameter includes a plurality of times for a respective plurality of memory operations of the non-volatile memory device, wherein the at least one reliability parameter includes a plurality of voltages for the respective plurality of memory operations of the non-volatile memory device. ### Claim 3 (depends on 2) The non-volatile memory device of claim 2, wherein the control logic is configured to read the first initial data stored in the first region in response to the initial data read command, and store the read first initial data in the initialization register. ### Claim 4 (depends on 3) The non-volatile memory device of claim 3, wherein the control logic is configured to read the second initial data in a second region selected from among the second regions in response to the initial data read command, and store the read second initial data in a portion of the initialization register. ### Claim 5 (depends on 3) The non-volatile memory device of claim 3, wherein the control logic is configured to read the second initial data stored in the second regions in response to the initial data read command, and store one among the different read second initial data in the initialization register. ### Claim 6 (depends on 2) The non-volatile memory device of claim 2, wherein the initial data read command comprises a first initial data read command and a second initial data read command. ### Claim 7 (depends on 6) The non-volatile memory device of claim 6, wherein the control logic is configured to read the first initial data stored in the first region in response to the first initial data read command, and read a second initial data stored in one among the second regions, in response to the second initial data read command. ### Claim 8 (depends on 1) The non-volatile memory device of claim 1, wherein the meta area comprises a plurality of meta blocks having a plurality of memory cells connected to a plurality of word-lines and a plurality of bit-lines, wherein meta block one of the plurality of meta blocks comprises the first region and the second region. ### Claim 9 (depends on 1) The non-volatile memory device of claim 1, wherein the meta area comprises a plurality of meta blocks having a plurality of memory cells connected to a plurality of word-lines and a plurality of bit-lines, wherein at least two meta blocks of the plurality of meta blocks comprise the first region and the second region. ### Claim 10 (depends on 1) The non-volatile memory device of claim 1, wherein the first initial data comprises at least one performance parameter related to the read operation, the program operation, or the erase operation, and wherein the second initial data comprises at least one reliability parameter related to the read operation, the program operation, or the erase operation. ### Claim 11 An operating method in a storage device having a non-volatile memory device and a controller controlling the non-volatile memory device, comprising: performing a power-up operation by supplying power; selecting an application usage after the power-up operation; reading initial data according to the application usage; and setting a register of the non-volatile memory device with the read initial data, wherein the reading initial data according to the application usage comprises: reading first initial data related to a core operation from the non-volatile memory device; and reading and updating second initial data, corresponding to the core operation, according to the application usage from the non-volatile memory device, wherein one of the first initial data or the second initial data comprises at least one performance parameter related to an operation time of at least one memory operation, wherein the other of the first initial data or the second initial data comprises at least one reliability parameter related to at least one of retention, endurance, voltage or verification of the at least one memory operation, wherein one of the first initial data or the second initial data is provided in common, and the other of the first initial data or the second initial data is selectable by a user. ### Claim 12 (depends on 11) The method of claim 11, further comprising transmitting an initialization operation request to the non-volatile memory device, wherein the at least one performance parameter includes a plurality of times for a respective plurality of memory operations, wherein the at least one reliability parameter includes a plurality of voltages for the respective plurality of memory operations. ### Claim 13 (depends on 12) The method of claim 12, wherein the initialization operation request comprises an initial data read command, a first address, and a second address, wherein the first address is an address indicating a region storing the first initial data, and wherein the second address is an address indicating a region storing the second initial data. ### Claim 14 (depends on 11) The method of claim 11, wherein the first initial data comprises a read time, a program time, or an erase time, for setting a memory operation. ### Claim 15 (depends on 11) The method of claim 11, further comprising performing a read operation, a program operation, or an erase operation using data set in the register of the non-volatile memory device. ### Claim 16 A non-volatile memory device comprising: a memory cell array having a plurality of memory blocks having a plurality of memory cells connected to a plurality of word-lines and a plurality of bit-lines; a row decoder configured to select a memory block, among the plurality of memory blocks, in response to an address; a voltage generator configured to apply word-line voltages corresponding to a selected word-line and unselected word-lines, among the plurality of word-lines; page buffers connected to the plurality of bit-lines and reading data from memory cells connected to the selected word-line of the selected memory block among the plurality of memory blocks; and control logic configured to control the row decoder, the voltage generator, and the page buffers, wherein at least one memory block, among the plurality of memory blocks, comprises a first region configured to store first initial data, and second regions configured to store second initial data, different from each other, and wherein the control logic is configured to read the first initial data stored in the first region and the second initial data stored in a second region, among the second regions, according to an initialization operation request, store the first initial data in an initialization register, and to store and update the second initial data in at least a portion of the initialization register, wherein one of the first initial data or the second initial data comprises at least one performance parameter related to an operation time of the non-volatile memory device, wherein the other of the first initial data or the second initial data comprises at least one reliability parameter related to at least one of retention, endurance, voltage or verification of the non-volatile memory device, wherein one of the first initial data or the second initial data is provided in common, and the other of the first initial data or the second initial data is selectable by a user. ### Claim 17 (depends on 16) The non-volatile memory device of claim 16, wherein the at least one memory block comprises single-level cells, wherein the at least one performance parameter includes a plurality of times for a respective plurality of memory operations, wherein the at least one reliability parameter includes a plurality of voltages for the respective plurality of memory operations. ### Claim 18 (depends on 16) The non-volatile memory device of claim 16, wherein the first initial data comprises a core condition related to a memory operation, and wherein the second initial data comprises an additional condition corresponding to the core condition. ### Claim 19 (depends on 18) The non-volatile memory device of claim 18, wherein the core condition comprises a plurality of core conditions, different from each other, wherein the plurality of core conditions are stored in regions, different from each other, separated by an address. ### Claim 20 (depends on 18) The non-volatile memory device of claim 18, wherein the additional condition comprises a plurality of additional conditions, different from each other, wherein the plurality of additional conditions are stored in regions, different from each other, separated by an address.