# US 12,217,800 B2 · Semiconductor device and data storage system including the same

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- Number: US 12,217,800 B2
- Document ID: US12217800B2
- Status: Granted
- Kind: B2
- Application number: 18/591,728
- Filed: 2024-02-29
- Published: 2024-07-25
- Granted: 2025-02-04
- Earliest claimed: 2020-11-19
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Samsung Electronics Co., Ltd.
- Inventors: Jaeho Ahn; Jiwon Kim; Sungmin Hwang; Joonsung Lim; Sukkang Sung
- Web page: https://patentgrep.com/patent/US12217800B2

## CPC

- G11C 16/10: Programming or data input circuits
- H10W 20/023: {the interconnections being through-semiconductor vias}
- G11C 16/26: Sensing or reading circuits; Data output circuits
- H10B 41/27: the channels comprising vertical portions, e.g. U-shaped channels
- H10B 41/35: with a cell select transistor, e.g. NAND
- H10B 41/40: characterised by the peripheral circuit region
- H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels
- H10B 43/35: with cell select transistors, e.g. NAND
- H10B 43/40: characterised by the peripheral circuit region
- H10B 43/50: characterised by the boundary region between the core and peripheral circuit regions
- H10W 20/0238: {comprising etching via holes through pads or through electrodes}
- H10W 20/0242: {comprising etching via holes from the back sides of the chips, wafers or substrates}
- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10W 20/2125: {Top-view shapes}
- G11C 16/0483: {comprising cells having several storage transistors connected in series}
- H10W 72/884: {Die-attach connectors and bond wires}
- H10W 90/792: {between multiple chips}
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

A semiconductor memory device includes: a semiconductor substrate having a first surface and a second surface opposing each other; a back-side insulating layer below the second surface of the semiconductor substrate; an external input/output conductive pattern below the back-side insulating layer; a circuit device including a gate electrode and a source/drain region, on the first surface of the semiconductor substrate; an internal input/output conductive pattern on the first surface of the semiconductor substrate, the internal input/output conductive pattern having at least a portion disposed on the same level as at least a portion of the gate electrode; a through-electrode structure penetrating through the semiconductor substrate and the back-side insulating layer and electrically connected to the internal input/output conductive pattern and the external input/output conductive pattern; and a memory cell array region disposed on a level higher than the circuit device, on the first surface of the semiconductor substrate.

## Claims

### Claim 1

A semiconductor device comprising:
a first chip structure; and
a second chip structure on the first chip structure and including a memory cell array region,
wherein the first chip structure includes:
a semiconductor substrate having a first surface and a second surface opposing each other;
a back side insulating layer below the second surface of the semiconductor substrate;
an external input/output conductive pattern below the back side insulating layer;
a first active region on the first surface of the semiconductor substrate;
an isolation layer on the first surface of the semiconductor substrate and a side surface of the first active region;
a transistor including a source/drain region within a first portion of the first active region and a gate structure on a second portion of the first active region;
an interlayer insulating layer on the first active region and the isolation layer;
an input/output connection wiring on the interlayer insulating layer;
a first input/output contact plug penetrating through the interlayer insulating layer and electrically connected to the input/output connection wiring; and
a through-electrode structure penetrating through the semiconductor substrate and the back side insulating layer and electrically connected to the first input/output contact plug and the external input/output conductive pattern,
wherein the through-electrode structure includes a through-electrode and an insulating spacer on a side surface of the through-electrode,
wherein an upper end of the through-electrode is at a higher level than an upper end of the insulating spacer, and
wherein the through-electrode contacts the first input/output contact plug.

### Claim 2 (depends on 1)

The semiconductor device of claim 1,
wherein a lower end of the first input/output contact plug is at a lower level than an upper surface of the isolation layer.

### Claim 3 (depends on 1)

The semiconductor device of claim 1,
wherein a side surface of the first input/output contact plug includes:
a lower side portion contacting the through-electrode; and
an upper side portion contacting the interlayer insulating layer.

### Claim 4 (depends on 3)

The semiconductor device of claim 3,
wherein the through-electrode includes an electrode pattern and an electrode barrier layer covering a side surface and an upper surface of the electrode pattern, and
wherein the electrode barrier layer contacts a lower surface of the first input/output contact plug and the lower side portion of the first input/output contact plug.

### Claim 5 (depends on 4)

The semiconductor device of claim 4,
wherein the first input/output contact plug includes a plug pattern and a plug barrier layer on a side surface and a lower surface of the plug pattern.

### Claim 6 (depends on 4)

The semiconductor device of claim 4,
wherein the first input/output contact plug includes a plug pattern and a plug barrier layer on a side surface of an upper portion of the plug pattern, and
wherein a lower end of the plug pattern is at a lower level than a lower end of the plug barrier layer.

### Claim 7 (depends on 1)

The semiconductor device of claim 1,
wherein the through-electrode structure penetrates through the isolation layer.

### Claim 8 (depends on 1)

The semiconductor device of claim 1,
wherein the first chip structure further includes a dummy active region on the first surface of the semiconductor substrate and defined by the isolation layer, and
wherein the through-electrode structure penetrates through the dummy active region.

### Claim 9 (depends on 1)

The semiconductor device of claim 1,
wherein the first chip structure further includes an insulating liner on the first active region and the isolation layer and below the interlayer insulating layer,
wherein the insulating liner includes a material different from a material of the interlayer insulating layer, and
wherein a thickness of the interlayer insulating layer is greater than a thickness of the insulating liner.

### Claim 10 (depends on 9)

The semiconductor device of claim 9,
wherein the through-electrode penetrates through the insulating liner and contacts the interlayer insulating layer.

### Claim 11 (depends on 9)

The semiconductor device of claim 9,
wherein the insulating spacer contacts the insulating liner and is spaced apart from the interlayer insulating layer.

### Claim 12 (depends on 1)

The semiconductor device of claim 1,
wherein the first chip structure further includes a second input/output contact plug penetrating through the interlayer insulating layer and electrically connected to the input/output connection wiring and the through-electrode, and
wherein the second input/output contact plug is spaced apart from the first input/output contact plug.

### Claim 13 (depends on 1)

The semiconductor device of claim 1,
wherein the first chip structure further includes:
a circuit wiring on the interlayer insulating layer; and
a source/drain contact plug penetrating through the interlayer insulating layer and electrically connected to the source/drain region and the circuit wiring, and
wherein the circuit wiring is at the same level as the input/output connection wiring.

### Claim 14 (depends on 13)

The semiconductor device of claim 13,
wherein an upper surface of the source/drain contact plug is at the same level as the first input/output contact plug.

### Claim 15

A semiconductor device comprising:
a first chip structure; and
a second chip structure on the first chip structure and including a memory cell array region,
wherein the first chip structure includes:
a semiconductor substrate having a first surface and a second surface opposing each other;
a back side insulating layer below the second surface of the semiconductor substrate;
an external input/output conductive pattern below the back side insulating layer;
a first active region on the first surface of the semiconductor substrate;
an isolation layer on the first surface of the semiconductor substrate and a side surface of the first active region;
a transistor including a source/drain region within a first portion of the first active region and a gate structure on a second portion of the first active region;
an interlayer insulating layer on the first active region and the isolation layer;
an input/output connection wiring and a circuit wiring on the interlayer insulating layer;
a source/drain contact plug penetrating through the interlayer insulating layer and electrically connected to the source/drain region and the circuit wiring;
a first input/output contact plug penetrating through the interlayer insulating layer and electrically connected to the input/output connection wiring; and
a through-electrode structure penetrating through the semiconductor substrate and the back side insulating layer and electrically connected to the first input/output contact plug and the external input/output conductive pattern,
wherein the through-electrode structure includes a through-electrode and an insulating spacer on a side surface of the through-electrode,
wherein a width of the through-electrode is greater than a width of the first input/output contact plug, and
wherein a side surface of the first input/output contact plug includes:
a lower side portion contacting the through-electrode; and
an upper side portion contacting the interlayer insulating layer,
wherein the through-electrode includes an electrode pattern and an electrode barrier layer covering a side surface and an upper surface of the electrode pattern, and
wherein the electrode barrier layer contacts a lower surface of the first input/output contact plug and the lower side portion of the first input/output contact plug.

### Claim 16 (depends on 15)

The semiconductor device of claim 15,
wherein the first chip structure further includes an insulating liner on the first active region and the isolation layer and below the interlayer insulating layer,
wherein the insulating liner includes a material different from a material of the interlayer insulating layer,
wherein a thickness of the interlayer insulating layer is greater than a thickness of the insulating liner, and
wherein the through-electrode penetrates through the insulating liner and contacts the interlayer insulating layer.

### Claim 17 (depends on 16)

The semiconductor device of claim 16,
wherein the insulating spacer contacts the insulating liner and is spaced apart from the interlayer insulating layer.

### Claim 18

A data storage system comprising:
a main substrate;
a semiconductor device on the main substrate; and
a controller electrically connected to the semiconductor device on the main substrate,
wherein the semiconductor device includes:
a first chip structure; and
a second chip structure on the first chip structure and including a memory cell array region,
wherein the first chip structure includes:
a semiconductor substrate having a first surface and a second surface opposing each other;
a back side insulating layer below the second surface of the semiconductor substrate;
an external input/output conductive pattern below the back side insulating layer;
a first active region on the first surface of the semiconductor substrate;
an isolation layer on the first surface of the semiconductor substrate and a side surface of the first active region;
a transistor including a source/drain region within a first portion of the first active region and a gate structure on a second portion of the first active region;
an interlayer insulating layer on the first active region and the isolation layer;
an input/output connection wiring and a circuit wiring on the interlayer insulating layer;
a source/drain contact plug penetrating through the interlayer insulating layer and electrically connected to the source/drain region and the circuit wiring;
a first input/output contact plug penetrating through the interlayer insulating layer and electrically connected to the input/output connection wiring; and
a through-electrode structure penetrating through the semiconductor substrate and the back side insulating layer and electrically connected to the first input/output contact plug and the external input/output conductive pattern,
wherein the through-electrode structure includes a through-electrode and an insulating spacer on a side surface of the through-electrode,
wherein a width of the through-electrode is greater than a width of the first input/output contact plug, and
wherein a side surface of the first input/output contact plug includes:
a lower side portion contacting the through-electrode; and
an upper side portion contacting the interlayer insulating layer,
wherein the through-electrode includes an electrode pattern and an electrode barrier layer covering a side surface and an upper surface of the electrode pattern, and
wherein the electrode barrier layer contacts a lower surface of the first input/output contact plug and the lower side portion of the first input/output contact plug.

### Claim 19 (depends on 18)

The data storage system of claim 18,
wherein an upper end of the through-electrode is at a higher level than an upper end of the insulating spacer, and
wherein the through-electrode contacts the first input/output contact plug.

### Claim 20 (depends on 18)

The data storage system of claim 18,
wherein a lower end of the first input/output contact plug is at a lower level than an upper surface of the isolation layer, and
wherein an upper end of the through-electrode is at a higher level than the upper surface of the isolation layer.