# US 12,217,798 B2 · Bank design with differential bulk bias in eFuse array > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,217,798 B2 - Document ID: US12217798B2 - Status: Granted - Kind: B2 - Application number: 18/362,198 - Filed: 2023-07-31 - Published: 2023-11-23 - Granted: 2025-02-04 - Earliest claimed: 2021-04-16 - Assignees: Taiwan Semiconductor Manufacturing Company, Ltd. - Applicants: Taiwan Semiconductor Manufacturing Company, Ltd. - Inventors: Meng-Sheng Chang; Chia-En Huang - Web page: https://patentgrep.com/patent/US12217798B2 ## CPC - G11C 16/0483: {comprising cells having several storage transistors connected in series} - G11C 17/16: using electrically-fusible links - G11C 16/12: Programming voltage switching circuits - G11C 17/165: {Memory cells which are electrically programmed to cause a change in resistance, e.g. to permit multiple resistance steps to be programmed rather than conduct to or from non-conduct change of fuses and antifuses (digital stores using resistance random access memory elements G11C13/0002)} - H10B 20/25: One-time programmable ROM [OTPROM] devices, e.g. using electrically-fusible links - G11C: STATIC STORES (semiconductor memory devices H10B) - H10B: ELECTRONIC MEMORY DEVICES ## Abstract A memory circuit includes a first memory cell including a first resistor; and a first transistor coupled to the first resistor, wherein a first bulk port of the first transistor is biased at a first voltage level; a second memory cell coupled to the first memory cell, the second memory cell including a second resistor; and a second transistor coupled to the second memory cell, wherein a second bulk port of the second transistor is biased at a second voltage level, wherein the second voltage level is less than the first voltage level. ## Claims ### Claim 1 A memory circuit comprising: a plurality of memory cells, each of the plurality of memory cells including a resistor and a transistor coupled to each other in series; and a sensing circuit including a read access transistor coupled to each of the plurality of memory cells, wherein respective bulk ports of the transistors of at least a first memory cell and a second memory cell of the plurality of memory cells are biased at different voltage levels, wherein, in response to the read access transistor receiving a read bit line voltage, the sensing circuit is configured to sense at least one of the first memory cell or the second memory cell. ### Claim 2 (depends on 1) The memory circuit of claim 1, wherein the first memory cell o comprises a first electronic fuse (eFuse). ### Claim 3 (depends on 2) The memory circuit of claim 2, wherein the second memory cell comprises a second eFuse. ### Claim 4 (depends on 2) The memory circuit of claim 2, wherein in response to the sensing circuit sensing the first eFuse, the first eFuse provides a signal having a voltage level of zero volts. ### Claim 5 (depends on 1) The memory circuit of claim 1, wherein a first bulk port of the transistor of the first memory cell is biased at a first voltage level. ### Claim 6 (depends on 5) The memory circuit of claim 5, wherein a second bulk port of the transistor of the second memory cell is biased at a second voltage level that is less than the first voltage level. ### Claim 7 (depends on 1) The memory circuit of claim 1, wherein the transistor of the first memory cell is a deep n-well (DNW) transistor and the transistor of the second memory cell is a bulk transistor. ### Claim 8 (depends on 1) The memory circuit of claim 1, wherein the transistor of the first memory cell and the transistor of the second memory cell are each deep n-well (DNW) transistors. ### Claim 9 (depends on 1) The memory circuit of claim 1, further comprising a write access transistor coupled to each of the first memory cell and the second memory cell. ### Claim 10 (depends on 1) The memory circuit of claim 1, wherein, in response to the write access transistor receiving a write bit line voltage, a voltage source coupled to the write access transistor programs at least one of the first memory cell or the second memory cell. ### Claim 11 (depends on 1) The memory circuit of claim 1, wherein the first memory cell and the second memory cell are each in series with a second resistor. ### Claim 12 A memory circuit comprising: a plurality of memory cells, each of the plurality of memory cells including a resistor and a transistor coupled to each other in series; and a write access transistor coupled to each of the plurality of memory cells, wherein respective bulk ports of the transistors of at least a first memory cell and a second memory cell of the plurality of memory cells are biased at different voltage levels, wherein, in response to the write access transistor receiving a write bit line voltage, a voltage source coupled to the write access transistor programs at least one of the first memory cell or the second memory cell. ### Claim 13 (depends on 12) The memory circuit of claim 12, wherein the first memory cell is a first electronic fuse (eFuse) and the second memory cell is a second eFuse. ### Claim 14 (depends on 13) The memory circuit of claim 13, wherein the first eFuse is not programmed and the second eFuse is programmed. ### Claim 15 (depends on 13) The memory circuit of claim 13, further comprising a sensing circuit coupled to the first eFuse, wherein, in response to the sensing circuit sensing the first eFuse, the first eFuse provides a signal having a voltage level of zero volts. ### Claim 16 (depends on 12) The memory circuit of claim 12, wherein the resistor of the first memory cell is coupled to first routing having a first resistance and the resistor of the second memory cell is coupled to second routing having a second resistance greater than the first resistance. ### Claim 17 (depends on 12) The memory circuit of claim 12, wherein the transistor of the first memory cell is a deep n-well (DNW) transistor and the transistor of the second memory cell is a bulk transistor. ### Claim 18 (depends on 12) The memory circuit of claim 12, wherein the transistor of the first memory cell and the transistor of the second memory cell are each deep n-well (DNW) transistors. ### Claim 19 A memory device comprising: a substrate including a first portion and a second portion disposed over the first portion; a first bulk electrode of a first word line (WL) transistor disposed over the second portion of the substrate; a deep n-well disposed over the first portion of the substrate; a pair of n-wells disposed over the deep n-well; a p-well disposed over the deep n-well and in between the pair of n-wells; a second bulk electrode of a second word line (WL) transistor disposed over the p-well; and a write access transistor coupled to each of the first bulk electrode and the second bulk electrode, wherein, in response to the write access transistor receiving a write bit line voltage, a voltage source coupled to the write access transistor provides a voltage signal to the first bulk electrode and the second bulk electrode. ### Claim 20 (depends on 19) The memory device of claim 19, further comprising a third bulk electrode of the second WL transistor disposed over a third portion of the substrate.