# US 12,217,795 B2 · Memory and operating method thereof

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- Number: US 12,217,795 B2
- Document ID: US12217795B2
- Status: Granted
- Kind: B2
- Application number: 18/595,188
- Filed: 2024-03-04
- Published: 2024-06-20
- Granted: 2025-02-04
- Earliest claimed: 2021-07-30
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.; National Tsing Hua University
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.; National Tsing Hua University
- Inventors: Meng-Fan Chang; Yen-Cheng Chiu
- Web page: https://patentgrep.com/patent/US12217795B2

## CPC

- G11C 13/004: {Reading or sensing circuits or methods}
- G11C 7/067: {Single-ended amplifiers}
- G11C 11/5678: {using amorphous/crystalline phase transition storage elements}
- G11C 13/0004: {comprising amorphous/crystalline phase transition cells}
- G11C 7/08: Control thereof
- H03K 19/20: characterised by logic function, e.g. AND, OR, NOR, NOT circuits (H03K19/003 - H03K19/01 take precedence)
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)

## Abstract

A memory includes a memory device, a reading device and a feedback device. The memory device stores a plurality of bits. The reading device includes first and second reading circuits coupled to the memory device. The second reading circuit is coupled to the first reading circuit at a first node. The first and second reading circuits cooperates with each other to generate a first voltage signal at the first node based on at least one first bit of the plurality of bits. The feedback device adjusts at least one of the first reading circuit or the second reading circuit based on the first voltage signal. The first and second reading circuits generate a second voltage signal, different from the first voltage signal, corresponding to the bits, after the at least one of the first reading circuit or the second reading circuit is adjusted by the feedback device.

## Claims

### Claim 1

A device, comprising:
a memory device configured to store a plurality of bits;
a first switch coupled to the memory device at a first node;
a second switch configured to control the first switch; and
a feedback device configured to adjust the second switch based on a first voltage signal generated at the first node,
wherein each of the first switch and the second switch is configured to receive a reference voltage signal, and
the first voltage signal is generated based on the plurality of bits.

### Claim 2 (depends on 1)

The device of claim 1, further comprising:
a third switch configured to provide an enable voltage signal to a control terminal of the first switch according to a control signal; and
a fourth switch coupled in parallel with the first switch and configured to receive the enable voltage signal,
wherein a control terminal of the second switch is configured to receive the control signal.

### Claim 3 (depends on 2)

The device of claim 2, wherein the feedback device comprises:
an inverter configured to output the control signal, an input terminal of the inverter being coupled to a control terminal of the third switch.

### Claim 4 (depends on 1)

The device of claim 1, further comprising:
a third switch coupled in series with the first switch at the first node; and
a fourth switch configured to control the first switch,
wherein the feedback device is further configured to adjust the second switch based on the first voltage signal.

### Claim 5 (depends on 4)

The device of claim 4, wherein the feedback device comprises:
a first logic unit configured generate a control signal and receive a reference voltage signal,
wherein the fourth switch is further configured to provide the reference voltage signal to a control terminal of the third switch according to the control signal.

### Claim 6 (depends on 5)

The device of claim 5, wherein the feedback device further comprises:
a second logic unit configured to control the second switch and receive the reference voltage signal,
wherein a logic type of the first logic unit is same as a logic type of the second logic unit.

### Claim 7 (depends on 5)

The device of claim 5, further comprising:
a sensing device configured to generate a first digital signal according to the first voltage signal,
wherein two input terminals of the first logic unit are configured to receive the first digital signal and the reference voltage signal, respectively.

### Claim 8 (depends on 7)

The device of claim 7, wherein in response to a most significant bit of the plurality of bits having a first bit value, the first digital signal has a second bit value different from the first bit value, and
in response to the most significant bit having the second bit value, the first digital signal has the first bit value.

### Claim 9

A device, comprising:
a memory device;
a first reading circuit coupled to the memory device, and configured to generate a first voltage signal based on data stored in the memory device; and
a first logic unit configured to adjust the first reading circuit based on the first voltage signal,
wherein the first reading circuit is configured to generate a second voltage signal, different from the first voltage signal, corresponding to the data, after the first reading circuit is adjusted by the first logic unit.

### Claim 10 (depends on 9)

The device of claim 9, further comprising:
a second reading circuit configured to generate the first voltage signal with the first reading circuit;
a second logic unit configured to adjust the second reading circuit based on the first voltage signal; and
a sensing device configured to generate a first digital signal and a second digital signal according to the first voltage signal,
wherein the first logic unit and the second logic unit are configured to receive the first digital signal and the second digital signal, respectively.

### Claim 11 (depends on 10)

The device of claim 10, wherein the first digital signal and the second digital signal are complemented from each other.

### Claim 12 (depends on 11)

The device of claim 11, wherein a bit value of the first digital signal is same as a most significant bit of the data.

### Claim 13 (depends on 10)

The device of claim 10, wherein the second reading circuit comprises:
a first switch coupled between the sensing device and the memory device; and
a second switch configured to provide a reference voltage signal to a control terminal of the first switch,
wherein the second logic unit is further configured to control the second switch and receive the reference voltage signal.

### Claim 14 (depends on 13)

The device of claim 13, wherein the first logic unit is further configured to receive the reference voltage signal.

### Claim 15 (depends on 9)

The device of claim 9, wherein the first reading circuit comprises:
a first switch and a second switch coupled in parallel between a first node and a second node;
a third switch coupled between a control terminal of the first switch and the second node; and
a fourth switch coupled between a control terminal of the second switch and the second node,
wherein the first voltage signal is generated at the first node.

### Claim 16 (depends on 15)

The device of claim 15, further comprising:
a sensing device configured to generate a first digital signal and a second digital signal according to the first voltage signal; and
a second logic unit configured to control the fourth switch according to each of the first digital signal and the second digital signal,
wherein the first logic unit is configured to control the third switch according to the first digital signal.

### Claim 17 (depends on 16)

The device of claim 16, wherein
in response to two most significant bit of the data having a first bit value, the first digital signal and the second digital signal have a first value and a second value, respectively,
in response to the two most significant bit having a second bit value, the first digital signal and the second digital signal have the second value and the first value, respectively,
in response to the two most significant bit having a third bit value, each of the first digital signal and the second digital signal has the second value,
the first bit value, the second bit value and the third bit value are different from each other, and
the first value is different from the second value.

### Claim 18

A method, comprising:
generating a first voltage signal at a first node according to data;
generating a first control signal based on the first voltage signal;
inverting the first control signal to generate a second control signal;
receiving each of the first control signal and the second control signal by a first switch;
controlling a second switch by the first switch; and
generating, corresponding to the data, a second voltage signal at the first node by the second switch.

### Claim 19 (depends on 18)

The method of claim 18, wherein generating the first control signal comprises:
sensing the first voltage signal to generate a digital signal indicating a most significant bit of the data; and
generating the first control signal according to the digital signal.

### Claim 20 (depends on 18)

The method of claim 18, further comprising:
providing a reference voltage signal to the first node; and
providing the reference voltage signal to a control terminal of the second switch according to the second control signal.