# US 12,217,794 B2 · Managing the programming of an open translation unit > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,217,794 B2 - Document ID: US12217794B2 - Status: Granted - Kind: B2 - Application number: 18/425,619 - Filed: 2024-01-29 - Published: 2024-05-23 - Granted: 2025-02-04 - Earliest claimed: 2021-12-23 - Assignees: Micron Technology, Inc. - Applicants: Micron Technology, Inc. - Inventors: Murong Lang; Zhenming Zhou; Jian Huang; Tingjun Xie; Jiangli Zhu; Nagendra Prasad Ganesh Rao; Sead Zildzic - Web page: https://patentgrep.com/patent/US12217794B2 ## CPC - G11C 11/5628: {Programming or writing circuits; Data input circuits} - G11C 16/10: Programming or data input circuits - G11C 7/04: with means for avoiding disturbances due to temperature effects - G11C 11/5671: {using charge trapping in an insulator} - G11C 16/0483: {comprising cells having several storage transistors connected in series} - G11C 16/08: Address circuits; Decoders; Word-line control circuits - G11C 16/32: Timing circuits - G11C 16/3418: {Disturbance prevention or evaluation; Refreshing of disturbed memory data} - G11C 16/3427: {Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written} - G11C 16/3459: {Circuits or methods to verify correct programming of nonvolatile memory cells} - G11C 29/021: {in voltage or current generators} - G11C 29/028: {with adaption or trimming of parameters} - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract A difference between a recorded time stamp for a first set of memory cells comprised by an open translation unit (TU) of memory cells and a current time stamp for the open TU is determined, wherein the first set of memory cells comprises a most recently programmed set of memory cells. It is determined, based on a current temperature for the open TU and the difference between the recorded time stamp and the current time stamp, that a second set of memory cells comprised by the open TU is in a coarse programming state. A programming operation is performed on the second set of memory cells using a reduced programming state verify level and a reduced programming state gate step size associated with the second set of memory cells. ## Claims ### Claim 1 A system comprising: a memory device; and a processing device, operatively coupled with the memory device, to perform operations comprising: determining a difference between a recorded time stamp for a first set of memory cells comprised by an open translation unit (TU) of memory cells and a current time stamp for the open TU, wherein the first set of memory cells comprises a most recently programmed set of memory cells; determining, based on a current temperature for the open TU and the difference between the recorded time stamp and the current time stamp, that a second set of memory cells comprised by the open TU is in a coarse programming state; and performing, using a reduced programming state verify level and a reduced programming state gate step size associated with the second set of memory cells, a programming operation on the second set of memory cells. ### Claim 2 (depends on 1) The system of claim 1, wherein the processing device is to perform operations further comprising: identifying a third set of memory cells, wherein the third set of memory cells is comprised by the open TU; and performing, using a programming state verify level associated with the third set of memory cells and a programming state gate step size associated with each wordline (WL) of the open TU, a programming operation on the third set of memory cells. ### Claim 3 (depends on 1) The system of claim 1, wherein the processing device is to perform operations further comprising: in response to determining that the current temperature for the open TU and the difference between the recorded time stamp and the current time stamp do not satisfy a threshold criterion, performing, using a programming state verify level associated with the second set of memory cells and a programming state gate step size associated with each wordline (WL) of the open TU, the programming operation on the second set of memory cells. ### Claim 4 (depends on 1) The system of claim 1, wherein the processing device is to perform operations further comprising: identifying a threshold voltage distribution shift for a first wordline (WL) based on a read operation to be performed on the first set of memory cells, wherein the first set of memory cells is addressable by the first WL. ### Claim 5 (depends on 1) The system of claim 1, wherein the processing device is to perform operations further comprising: identifying a threshold voltage distribution shift for a first wordline (WL) based on a trim operation to be performed on the first set of memory cells, wherein the first set of memory cells is addressable by the first WL. ### Claim 6 (depends on 1) The system of claim 1, wherein the processing device is to perform operations further comprising: recording the time stamp for the most recently programmed set of memory cells comprised by the open TU; recording the current time stamp for the open TU; and identifying the current temperature for the open TU. ### Claim 7 (depends on 1) The system of claim 1, wherein the processing device is to perform operations further comprising: determining, using a verify level offset, the reduced programming state verify level, wherein the verify level offset is scaled based on an amount of threshold voltage for each wordline (WL) of the open TU. ### Claim 8 (depends on 1) The system of claim 1, wherein the processing device is to perform operations further comprising: performing a programming operation on the first set of memory cells, wherein the first set of memory cells is addressable by a first wordline (WL). ### Claim 9 A method comprising: determining a difference between a recorded time stamp for a first set of memory cells comprised by an open translation unit (TU) of memory cells and a current time stamp for the open TU, wherein the first set of memory cells comprises a most recently programmed set of memory cells; determining, based on a current temperature for the open TU and the difference between the recorded time stamp and the current time stamp, that a second set of memory cells comprised by the open TU is in a coarse programming state; and performing, using a reduced programming state verify level and a reduced programming state gate step size associated with the second set of memory cells, a programming operation on the second set of memory cells. ### Claim 10 (depends on 9) The method of claim 9, further comprising: identifying a third set of memory cells, wherein the third set of memory cells is comprised by the open TU; and performing, using a programming state verify level associated with the third set of memory cells and a programming state gate step size associated with each wordline (WL) of the open TU, a programming operation on the third set of memory cells. ### Claim 11 (depends on 9) The method of claim 9, further comprising: in response to determining that the current temperature for the open TU and the difference between the recorded time stamp and the current time stamp do not satisfy a threshold criterion, performing, using a programming state verify level associated with the second set of memory cells and a programming state gate step size associated with each wordline (WL) of the open TU, the programming operation on the second set of memory cells. ### Claim 12 (depends on 9) The method of claim 9, further comprising: identifying a threshold voltage distribution shift for a first wordline (WL) based on a read operation to be performed on the first set of memory cells, wherein the first set of memory cells is addressable by the first WL. ### Claim 13 (depends on 9) The method of claim 9, further comprising: identifying a threshold voltage distribution shift for a first wordline (WL) based on a trim operation to be performed on the first set of memory cells, wherein the first set of memory cells is addressable by the first WL. ### Claim 14 (depends on 9) The method of claim 9, further comprising: recording the time stamp for the most recently programmed set of memory cells comprised by the open TU; recording the current time stamp for the open TU; and identifying the current temperature for the open TU. ### Claim 15 (depends on 9) The method of claim 9, further comprising: determining, using a verify level offset, the reduced programming state verify level, wherein the verify level offset is scaled based on an amount of threshold voltage for each wordline (WL) of the open TU. ### Claim 16 A non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to perform operations comprising: determining a difference between a recorded time stamp for a first set of memory cells comprised by an open translation unit (TU) of memory cells and a current time stamp for the open TU, wherein the first set of memory cells comprises a most recently programmed set of memory cells; determining, based on a current temperature for the open TU and the difference between the recorded time stamp and the current time stamp, that a second set of memory cells comprised by the open TU is in a coarse programming state; and performing, using a reduced programming state verify level and a reduced programming state gate step size associated with the second set of memory cells, a programming operation on the second set of memory cells. ### Claim 17 (depends on 16) The non-transitory computer-readable storage medium of claim 16, wherein the processing device is to perform operations further comprising: identifying a third set of memory cells, wherein the third set of memory cells is comprised by the open TU; and performing, using a programming state verify level associated with the third set of memory cells and a programming state gate step size associated with each wordline (WL) of the open TU, a programming operation on the third set of memory cells. ### Claim 18 (depends on 16) The non-transitory computer-readable storage medium of claim 16, wherein the processing device is to perform operations further comprising: in response to determining that the current temperature for the open TU and the difference between the recorded time stamp and the current time stamp do not satisfy a threshold criterion, performing, using a programming state verify level associated with the second set of memory cells and a programming state gate step size associated with each wordline (WL) of the open TU, the programming operation on the second set of memory cells. ### Claim 19 (depends on 16) The non-transitory computer-readable storage medium of claim 16, wherein the processing device is to perform operations further comprising: identifying a threshold voltage distribution shift for a first wordline (WL) based on a read operation to be performed on the first set of memory cells, wherein the first set of memory cells is addressable by the first WL. ### Claim 20 (depends on 16) The non-transitory computer-readable storage medium of claim 16, wherein the processing device is to perform operations further comprising: identifying a threshold voltage distribution shift for a first wordline (WL) based on a trim operation to be performed on the first set of memory cells, wherein the first set of memory cells is addressable by the first WL.