# US 12,217,793 B2 · Data transfer circuits in nonvolatile memory devices and nonvolatile memory devices including the same

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- Number: US 12,217,793 B2
- Document ID: US12217793B2
- Status: Granted
- Kind: B2
- Application number: 17/852,035
- Filed: 2022-06-28
- Published: 2023-05-18
- Granted: 2025-02-04
- Earliest claimed: 2021-11-16
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Samsung Electronics Co., Ltd.
- Inventors: Eunjin Song; Kyoungtae Kang; Sanglok Kim; Chiweon Yoon; Byunghoon Jeong
- Web page: https://patentgrep.com/patent/US12217793B2

## CPC

- G11C 7/1096: {Write circuits, e.g. I/O line write drivers}
- G11C 11/4096: Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
- G11C 7/1069: {I/O lines read out arrangements}
- G11C 11/4074: Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
- G11C 11/4093: Input/output [I/O] data interface arrangements, e.g. data buffers
- G11C 11/4094: Bit-line management or control circuits
- G11C 16/08: Address circuits; Decoders; Word-line control circuits
- G11C 16/10: Programming or data input circuits
- G11C 16/26: Sensing or reading circuits; Data output circuits
- G11C 5/025: {Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device (geometrical lay-out of the components in integrated circuits, geometrical lay-out of the components in integrated circuits H10D89/10)}
- G11C 16/0483: {comprising cells having several storage transistors connected in series}
- G11C 2207/107: Serial-parallel conversion of data or prefetch
- G11C 2211/5642: Multilevel memory with buffers, latches, registers at input or output
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

A data transfer circuit in a nonvolatile memory device includes first repeaters, second repeaters and signal lines. The signal lines connect the first repeaters and the second repeaters, and include a first group of signal lines and a second group of signal lines alternatingly arranged. The first repeaters include a first group of repeaters activated in a first operation mode and a second group of repeaters activated in a second operation mode. The second repeaters include a third group of repeaters activated in the first operation mode and are connected to the first group of repeaters through the first group of signal lines floated in the second operation mode, and a fourth group of repeaters activated in the second operation mode and are connected to the second group of repeaters through the second group of signal lines floated in the first operation mode.

## Claims

### Claim 1

A data transfer circuit in a nonvolatile memory device, the data transfer circuit comprising:
a plurality of first repeaters connected to a first circuit element disposed in a data input/output (I/O) path of the nonvolatile memory device;
a plurality of second repeaters connected to a second circuit element disposed in the data I/O path of the nonvolatile memory device, the second circuit element being spaced apart from the first circuit element; and
a plurality of signal lines configured to connect the plurality of first repeaters and the plurality of second repeaters, the plurality of signal lines including a first group of signal lines and a second group of signal lines which are alternatingly arranged,
wherein the plurality of first repeaters include:
a first group of repeaters that are activated in a first operation mode; and
a second group of repeaters that are activated in a second operation mode having a non-overlapping operating interval with the first operation mode,
wherein the plurality of second repeaters include:
a third group of repeaters that are activated in the first operation mode and are connected to the first group of repeaters through the first group of signal lines; and
a fourth group of repeaters that are activated in the second operation mode and are connected to the second group of repeaters through the second group of signal lines,
wherein the second group of signal lines are floated in the first operation mode, and
wherein the first group of signal lines are floated in the second operation mode.

### Claim 2 (depends on 1)

The data transfer circuit of claim 1, wherein, in the second operation mode,
the first group of repeaters are configured to float an output node coupled to the first group of signal lines in response to a first power gating signal; and
the third group of repeaters are configured to float an input node coupled to the first group of signal lines in response to the first power gating signal.

### Claim 3 (depends on 1)

The data transfer circuit of claim 1, wherein, in the first operation mode,
the second group of repeaters are configured to float an output node coupled to the second group of signal lines in response to a second power gating signal; and
the fourth group of repeaters are configured to float an input node coupled to the second group of signal lines in response to the second power gating signal.

### Claim 4 (depends on 1)

The data transfer circuit of claim 1, wherein each of the first group of repeaters and the third group of repeaters includes:
a first inverter connected between a power supply voltage and a first node;
a first discharge transistor connected between the first node and a ground voltage, the first discharge transistor having a gate to receive a first power gating signal;
a precharge transistor connected between the power supply voltage and a second node corresponding to an output of the first inverter, the precharge transistor having a gate to receive the first power gating signal;
a second inverter connected between the second node and an output node and between the power supply voltage and a third node; and
a second discharge transistor connected between the third node and the ground voltage, the second discharge transistor having a gate to receive the first power gating signal.

### Claim 5 (depends on 4)

The data transfer circuit of claim 4, wherein, in response to the first power gating signal having a logic high level in the first operation mode,
the first discharge transistor is configured to discharge the first node to the ground voltage, and
the second discharge transistor is configured to discharge the third node to the ground voltage.

### Claim 6 (depends on 4)

The data transfer circuit of claim 4, wherein the first inverter includes:
a first p-channel metal-oxide semiconductor (PMOS) transistor connected between the power supply voltage and the second node; and
a first n-channel metal-oxide semiconductor (NMOS) transistor connected between the second node and the first node,
wherein the second inverter includes:
a second PMOS transistor connected between the power supply voltage and the output node; and
a second NMOS transistor connected between the output node and the third node, and
wherein the first power gating signal has a logic low level in the second operation mode.

### Claim 7 (depends on 6)

The data transfer circuit of claim 6, wherein in response to the first power gating signal having a logic low level in the second operation mode,
the precharge transistor is configured to precharge the second node with the power supply voltage, and
the first NMOS transistor and the second NMOS transistor are turned off, and
the second PMOS transistor is turned off in response to a voltage level of the second node to float the output node coupled to a corresponding signal line from among the first group of signal lines.

### Claim 8 (depends on 1)

The data transfer circuit of claim 1, wherein each of the second group of repeaters and the fourth group of repeaters includes:
a first inverter connected between a power supply voltage and a first node;
a first discharge transistor connected between the first node and a ground voltage, the first discharge transistor having a gate to receive a second power gating signal;
a precharge transistor connected between the power supply voltage and a second node corresponding to an output of the first inverter, the precharge transistor having a gate to receive the second power gating signal;
a second inverter connected between the second node and an output node and between the power supply voltage and a third node; and
a second discharge transistor connected between the third node and the ground voltage, the second discharge transistor having a gate to receive the second power gating signal.

### Claim 9 (depends on 8)

The data transfer circuit of claim 8, wherein, in response to the second power gating signal having a logic high level in the second operation mode,
the first discharge transistor is configured to connect the first node to the ground voltage, and
the second discharge transistor is configured to connect the third node to the ground voltage.

### Claim 10 (depends on 8)

The data transfer circuit of claim 8, wherein the first inverter includes:
a first p-channel metal-oxide semiconductor (PMOS) transistor connected between the power supply voltage and the second node; and
a first n-channel metal-oxide semiconductor (NMOS) transistor connected between the second node and the first node,
wherein the second inverter includes:
a second PMOS transistor connected between the power supply voltage and the output node; and
a second NMOS transistor connected between the output node and the third node, and
wherein the second power gating signal has a logic low level in the first operation mode.

### Claim 11 (depends on 10)

The data transfer circuit of claim 10, wherein in response to the second power gating signal having a logic low level in the first operation mode,
the precharge transistor is configured to precharge the second node with the power supply voltage, and
the first NMOS transistor and the second NMOS transistor are turned off, and
the second PMOS transistor is turned off in response to a voltage level of the second node to float the output node coupled to a corresponding signal line from among the second group of signal lines.

### Claim 12 (depends on 1)

The data transfer circuit of claim 1, wherein:
the first circuit element includes a data input/output circuit configured to transmit/receive data to/from an external memory controller; and
the second circuit element includes a page buffer circuit coupled to a memory cell array including a plurality of memory blocks through a plurality of bit-lines.

### Claim 13

A nonvolatile memory device comprising:
a memory cell array including a plurality of memory cells;
a page buffer circuit coupled to the memory cell array through a plurality of bit-lines;
a data input/output (I/O) circuit configured to transmit/receive data to/from an external memory controller;
a data transfer circuit (i) comprising a plurality of first repeaters connected to the data I/O circuit and (ii) connected between the page buffer circuit and the data I/O circuit, configured to:
provide the data from the data I/O circuit to the page buffer circuit in a first operation mode; and
provide the data from the page buffer circuit to the data I/O circuit in a second operation mode having a non-overlapping operating interval with the first operation mode; and
a control circuit configured to control the page buffer circuit and the data transfer circuit,
wherein the data transfer circuit is configured to float a portion of signal lines that do not transfer the data, from among a plurality of signal lines included therein, in response to a first power gating signal and a second power gating signal from the control circuit in each of the first operation mode and the second operation mode, and
wherein the plurality of first repeaters include a first group of repeaters that are activated in the first operation mode and a second group of repeaters that are activated in the second operation mode.

### Claim 14 (depends on 13)

The nonvolatile memory device of claim 13, wherein the data transfer circuit includes:
a plurality of second repeaters connected to the page buffer circuit; and
a plurality of signal lines configured to connect the plurality of first repeaters and the plurality of second repeaters, the plurality of signal lines including a first group of signal lines and a second group of signal lines which are alternatingly arranged,
wherein the plurality of second repeaters include:
a third group of repeaters that are activated in the first operation mode and are connected to the first group of repeaters through the first group of signal lines; and
a fourth group of repeaters that are activated in the second operation mode and are connected to the second group of repeaters through the second group of signal lines,
wherein the second group of signal lines are floated in the first operation mode, and
wherein the first group of signal lines are floated in the second operation mode.

### Claim 15 (depends on 14)

The nonvolatile memory device of claim 14, wherein, in the second operation mode,
the first group of repeaters are configured to float a first output node coupled to the first group of signal lines in response to the first power gating signal; and
the third group of repeaters are configured to float an input node coupled to the first group of signal lines in response to the first power gating signal, and
wherein, in the first operation mode,
the second group of repeaters are configured to float a second output node coupled to the second group of signal lines in response to the second power gating signal; and
the fourth group of repeaters are configured to float an input node coupled to the second group of signal lines in response to the second power gating signal.

### Claim 16 (depends on 14)

The nonvolatile memory device of claim 14, wherein each of the first group of repeaters and the third group of repeaters includes:
a first inverter connected between a power supply voltage and a first node;
a first discharge transistor connected between the first node and a ground voltage, the first discharge transistor having a gate to receive a first power gating signal;
a precharge transistor connected between the power supply voltage and a second node corresponding to an output of the first inverter, the precharge transistor having a gate to receive the first power gating signal;
a second inverter connected between the second node and an output node and between the power supply voltage and a third node; and
a second discharge transistor connected between the third node and the ground voltage, the second discharge transistor having a gate to receive the first power gating signal.

### Claim 17 (depends on 14)

The nonvolatile memory device of claim 14, wherein each of the second group of repeaters and the fourth group of repeaters includes:
a first inverter connected between a power supply voltage and a first node;
a first discharge transistor connected between the first node and a ground voltage, the first discharge transistor having a gate to receive the second power gating signal;
a precharge transistor connected between the power supply voltage and a second node corresponding to an output of the first inverter, the precharge transistor having a gate to receive the second power gating signal;
a second inverter connected between the second node and an output node and between the power supply voltage and a third node; and
a second discharge transistor connected between the third node and the ground voltage, the second discharge transistor having a gate to receive the second power gating signal.

### Claim 18 (depends on 13)

The nonvolatile memory device of claim 13, wherein the page buffer circuit includes:
a plurality of page buffer units being disposed in a first horizontal direction; and
a plurality of cache latches being spaced apart from the plurality of page buffer units in the first horizontal direction, the plurality of cache latches respectively corresponding to the plurality of page buffer units, the plurality of cache latches commonly connected to a combined sensing node,
wherein each of the plurality of page buffer units includes a pass transistor connected to each sensing node and driven in response to a pass control signal.

### Claim 19 (depends on 13)

The nonvolatile memory device of claim 13, wherein:
the memory cell array is disposed on a first semiconductor layer;
the page buffer circuit, the data I/O circuit and the data transfer circuit are disposed on a second semiconductor layer; and
the first semiconductor layer and the second semiconductor layer are vertically stacked.

### Claim 20

A data transfer circuit in a nonvolatile memory device, the data transfer circuit comprising:
a plurality of first repeaters connected to a first circuit element disposed in a data input/output (I/O) path of the nonvolatile memory device;
a plurality of second repeaters connected to a second circuit element disposed in the data I/O path of the nonvolatile memory device, the second circuit element being spaced apart from the first circuit element; and
a plurality of signal lines configured to connect the plurality of first repeaters and the plurality of second repeaters, the plurality of signal lines including a first group of signal lines and a second group of signal lines which are alternatingly arranged,
wherein the plurality of first repeaters include:
a first group of repeaters that are activated in a first operation mode; and
a second group of repeaters that are activated in a second operation mode having a non-overlapping operating interval with the first operation mode,
wherein the plurality of second repeaters include:
a third group of repeaters that are activated in the first operation mode and are connected to the first group of repeaters through the first group of signal lines; and
a fourth group of repeaters that are activated in the second operation mode and are connected to the second group of repeaters through the second group of signal lines,
wherein, in the second operation mode, the first group of repeaters are configured to float a first output node coupled to the first group of signal lines in response to a first power gating signal, and
wherein, in the first operation mode, the second group of repeaters are configured to float a second output node coupled to the second group of signal lines in response to a second power gating signal.