# US 12,217,790 B2 · Memory array connections > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,217,790 B2 - Document ID: US12217790B2 - Status: Granted - Kind: B2 - Application number: 18/182,696 - Filed: 2023-03-13 - Published: 2023-12-21 - Granted: 2025-02-04 - Earliest claimed: 2022-06-21 - Assignees: Taiwan Semiconductor Manufacturing Company, Ltd. - Applicants: Taiwan Semiconductor Manufacturing Company, Ltd. - Inventors: Chieh Lee; Chia-En Huang; Chun-Ying Lee; Yi-Ching Liu; Yih Wang; Rose Tseng; Yao-Jen Yang; Jonathan Tsung-Yung Chang - Web page: https://patentgrep.com/patent/US12217790B2 ## CPC - G11C 5/025: {Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device (geometrical lay-out of the components in integrated circuits, geometrical lay-out of the components in integrated circuits H10D89/10)} - G11C 11/4091: Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating - G11C 5/06: Arrangements for interconnecting storage elements electrically, e.g. by wiring - G11C 11/4085: {Word line control circuits, e.g. word line drivers, - boosters, - pull-up, - pull-down, - precharge} - H10B 12/50: {Peripheral circuit region structures} - G11C 7/18: Bit line organisation; Bit line lay-out - G11C 11/16: using elements in which the storage effect is based on magnetic spin effect - G11C 11/4097: Bit-line organisation, e.g. bit-line layout, folded bit lines - G11C: STATIC STORES (semiconductor memory devices H10B) - H10B: ELECTRONIC MEMORY DEVICES ## Abstract A device includes a substrate, a first sense amplifier disposed on the substrate, a first word line driver disposed on the substrate and situated adjacent the first sense amplifier in the x-direction, and a first memory array disposed above the first sense amplifier and above the first word line driver in the z-direction. A plurality of first conductive segments extend alternately in the x-direction and the y-direction, and are disposed between the first memory array and the first sense amplifier and configured to electrically connect the first sense amplifier to a first bit line of the first memory array. A plurality of second conductive segments extend alternately in the x-direction and the y-direction, and are disposed between the first memory array and the first word line driver and configured to electrically connect the first word line driver to a first word line of the first memory array. ## Claims ### Claim 1 A device, comprising: a substrate; a first sense amplifier disposed on the substrate; a first word line driver disposed on the substrate and situated adjacent the first sense amplifier on the substrate in the x-direction; a first memory array disposed above the first sense amplifier and above the first word line driver in the z-direction; a plurality of first conductive segments that extend alternately in the x-direction and the y-direction, the plurality of first conductive segments disposed between the first memory array and the first sense amplifier and configured to electrically connect the first sense amplifier to a first bit line of the first memory array; and a plurality of second conductive segments that extend alternately in the x-direction and the y-direction, the plurality of second conductive segments disposed between the first memory array and the first word line driver and configured to electrically connect the first word line driver to a first word line of the first memory array. ### Claim 2 (depends on 1) The device of claim 1, wherein the first memory array has an array footprint that has a middle portion and a footprint boundary, and the first word line driver is situated in the middle portion of the array footprint and the first sense amplifier is situated near the footprint boundary of the array footprint. ### Claim 3 (depends on 1) The device of claim 1, wherein the first memory array has an array footprint that has a middle portion and a footprint boundary, and the first sense amplifier is situated in the middle portion of the array footprint and the first word line driver is situated near the footprint boundary of the array footprint. ### Claim 4 (depends on 1) The device of claim 1, wherein the first bit line of the first memory array is situated in the x-direction, along an x-axis, of the first memory array and the first word line of the first memory array is situated in the y-direction, along a y-axis, of the first memory array. ### Claim 5 (depends on 4) The device of claim 4, wherein the first bit line is connected to the first sense amplifier through a first conductive segment that extends in the y-direction, along the y-axis, and the first word line is connected to the first word line driver through a second conductive segment that extends in the x-direction, along the x-axis. ### Claim 6 (depends on 1) The device of claim 1, wherein the first word line of the first memory array is situated in the x-direction, along an x-axis, of the first memory array and the first bit line of the first memory array is situated in the y-direction, along a y-axis, of the memory array. ### Claim 7 (depends on 6) The device of claim 6, wherein the first word line is connected to the first word line driver through a first conductive segment that extends in the y-direction, along the y-axis, and the first bit line of the first memory array is connected to the first sense amplifier through a second conductive segment that extends in the x-direction, along the x-axis. ### Claim 8 (depends on 1) The device of claim 1, comprising: a second sense amplifier disposed on the substrate; a second word line driver disposed on the substrate and situated adjacent the second sense amplifier on the substrate in the x-direction; a second memory array disposed above the second sense amplifier and above the second word line driver in the z-direction; and a plurality of third conductive segments that extend alternately in the x-direction and the y-direction, the plurality of third conductive segments disposed between the second memory array and the first sense amplifier and configured to electrically connect the first sense amplifier to a second bit line of the second memory array. ### Claim 9 (depends on 8) The device of claim 8, comprising a plurality of fourth conductive segments that extend alternately in the x-direction and the y-direction, the plurality of fourth conductive segments disposed between the second memory array and the second sense amplifier and configured to electrically connect the second sense amplifier to a third bit line of the second memory array. ### Claim 10 (depends on 9) The device of claim 9, comprising a plurality of fifth conductive segments that extend alternately in the x-direction and the y-direction, the plurality of fifth conductive segments disposed between the first memory array and the second sense amplifier and configured to electrically connect the second sense amplifier to a fourth bit line of the first memory array. ### Claim 11 A device, comprising: a first memory array and a second memory array that is spaced apart from the first memory array in the x-direction; a first sense amplifier situated under the first memory array in the z-direction and a second sense amplifier situated under the second memory array in the z-direction; a plurality of first conductive segments that extend alternately in the x-direction and the y-direction, the plurality of first conductive segments disposed between the first memory array and the first sense amplifier and between the first memory array and the second sense amplifier and configured to electrically connect the first sense amplifier and the second sense amplifier to the first memory array; and a plurality of second conductive segments that extend alternately in the x-direction and the y-direction, the plurality of second conductive segments disposed between the second memory array and the first sense amplifier and between the second memory array and the second sense amplifier and configured to electrically connect the first sense amplifier and the second sense amplifier to the second memory array. ### Claim 12 (depends on 11) The device of claim 11, comprising a first word line driver situated under the first memory array in the z-direction and a second word line driver situated under the second memory array in the z-direction. ### Claim 13 (depends on 12) The device of claim 12, comprising a plurality of third conductive segments that extend alternately in the x-direction and the y-direction, the plurality of third conductive segments disposed between the first memory array and the first word line driver and configured to electrically connect the first word line driver to the first memory array. ### Claim 14 (depends on 13) The device of claim 13, comprising a plurality of fourth conductive segments that extend alternately in the x-direction and the y-direction, the plurality of fourth conductive segments disposed between the second memory array and the second word line driver and configured to electrically connect the second word line driver to the second memory array. ### Claim 15 (depends on 11) The device of claim 11, wherein the first memory array has an array footprint that has a middle portion and a footprint boundary, and the first word line driver is situated in the middle portion of the array footprint and the first sense amplifier is situated near the footprint boundary of the array footprint. ### Claim 16 (depends on 11) The device of claim 11, wherein the first memory array has an array footprint that has a middle portion and a footprint boundary, and the first sense amplifier is situated in the middle portion of the array footprint and the first word line driver is situated near the footprint boundary of the array footprint. ### Claim 17 A method of manufacturing a semiconductor device, the method comprising: forming front-end-of-line devices on a substrate of the semiconductor device; forming middle-end-of-line layers over the front-end-of-line devices in the z-direction; forming first back-end-of-line metal routing layers over the middle-end-of-line layers in the z-direction; forming back-end-of-line memory arrays adjacent each other in the x-direction and electrically connected to the first back-end-of-line metal routing layers; and forming second back-end-of-line metal routing layers over the back-end-of-line memory arrays in the z-direction. ### Claim 18 (depends on 17) The method of claim 17, wherein forming front-end-of-line devices includes: forming a first sense amplifier on the substrate; forming a first word line driver on the substrate adjacent the first sense amplifier on the substrate in the x-direction; forming a second sense amplifier on the substrate; and forming a second word line driver on the substrate adjacent the second sense amplifier on the substrate in the x-direction, wherein the first sense amplifier and the first word line driver are spaced apart from the second sense amplifier and the second word line driver in the x-direction. ### Claim 19 (depends on 18) The method of claim 18, wherein forming back-end-of-line memory arrays includes: forming a first memory array above the first sense amplifier and above the first word line driver in the z-direction; and forming a second memory array above the second sense amplifier and above the second word line driver in the z-direction. ### Claim 20 (depends on 19) The method of claim 19, wherein forming middle-end-of-line layers and forming first back-end-of-line metal routing layers includes forming conductive segments that extend alternately in the x-direction and the y-direction, the conductive segments configured to connect the first sense amplifier to each of the first memory array and the second memory array and to connect the second sense amplifier to each of the first memory array and the second memory array.