# US 12,217,787 B2 · Apparatus, system and method to detect and improve an input clock performance of a memory device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,217,787 B2 - Document ID: US12217787B2 - Status: Granted - Kind: B2 - Application number: 17/349,854 - Filed: 2021-06-16 - Published: 2021-10-07 - Granted: 2025-02-04 - Earliest claimed: 2021-06-16 - Assignees: Intel Corporation - Applicants: Intel Corporation - Inventors: Arvind A. Kumar; James Alexander McCall; Bill H. Nale; John R. Goles; Dean-Dexter R. Eugenio - Web page: https://patentgrep.com/patent/US12217787B2 ## CPC - G11C 11/4076: Timing circuits (for regeneration management G11C11/406) - G06F 13/1689: {Synchronisation and timing concerns (synchronisation on a memory bus G06F13/4234)} - G11C 5/04: Supports for storage elements {, e.g. memory modules}; Mounting or fixing of storage elements on such supports - G11C 7/222: {Clock generating, synchronizing or distributing circuits within memory device} - G11C 11/4072: Circuits for initialization, powering up or down, clearing memory or presetting - G11C 11/4074: Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits - G11C 11/4093: Input/output [I/O] data interface arrangements, e.g. data buffers - G11C 7/1057: {Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load} - G11C 7/225: {Clock input buffers} - G11C 2207/2254: Calibration - G11C: STATIC STORES (semiconductor memory devices H10B) - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract A method, apparatus and system. The method includes: performing one or more training iterations to tune a target clock signal frequency to be applied at a memory device, each of the one or more training iterations including: causing a modified clock signal frequency to be applied at the memory device; and decoding a quality feedback message from the memory device including an indication of a performance of the clock signal frequency at the memory device; and in response to a determination that the performance of the clock signal frequency falls within a target performance range of the memory device and that the clock signal frequency is below the target clock signal frequency, performing a subsequent training iteration of the one or more training iterations, and otherwise causing application at the memory device, during a memory operation, of a highest clock signal frequency corresponding to a training iteration for which performance of the clock signal was within the target performance range. ## Claims ### Claim 1 An integrated circuit of a memory subsystem including: an input and output (I/O) interface to connect to a memory device; one or more processors coupled to the I/O interface and configured to: perform one or more training iterations to tune a target clock signal frequency to be applied at the memory device, each of the one or more training iterations including: causing a modified clock signal frequency to be applied at the memory device; and decoding a quality feedback message from the memory device including an indication of a performance of the clock signal frequency at the memory device; and in response to a determination that the performance of the clock signal frequency falls within a target performance range of the memory device and that the clock signal frequency is below the target clock signal frequency, perform a subsequent training iteration of the one or more training iterations, and otherwise cause application at the memory device, during a memory operation, of a highest clock signal frequency corresponding to a training iteration for which performance of the clock signal was within the target performance range. ### Claim 2 (depends on 1) The integrated circuit of claim 1, wherein: the memory device is part of a memory module including a plurality of memory devices; the one or more processors are to perform the one or more training iterations to tune the target clock signal frequency to be applied at the memory devices; causing includes causing the modified clock signal frequency to be applied at the memory devices; and decoding a quality feedback message from the memory device includes decoding a respective quality feedback message from respective ones of the memory devices, each quality feedback message including an indication of a performance of the clock signal frequency at respective ones of the memory devices; and the one or more processors are further to, in response to a determination that the performance of the clock signal at said respective ones of the memory devices falls within a corresponding target performance range the respective ones of the memory devices, and that the clock signal frequency is below the target clock signal frequency, perform a subsequent training iteration of the one or more training iterations, and otherwise cause application at the memory devices, during memory operations, of a highest clock signal frequency corresponding to a training iteration for which performance of the clock signal was within target performance ranges of the memory devices. ### Claim 3 (depends on 2) The integrated circuit of claim 2, wherein the memory module includes a dual inline memory module (DIMM), and the memory devices include respective dynamic random access memories (DRAMs). ### Claim 4 (depends on 3) The integrated circuit of claim 3, wherein the DIMM includes a register coupled to the DRAMs, the one or more processors to cause the modified clock signal frequency to be applied by sending a command through the register to modify clock signal frequency at the DRAMs. ### Claim 5 (depends on 2) The integrated circuit of claim 2, wherein each of the one or more training iterations further includes modifying a termination level of at least one of the memory devices based on the clock signal frequency and prior to decoding. ### Claim 6 (depends on 1) The integrated circuit of claim 1, wherein the one or more training iterations include a plurality of training iterations, the one or more processors to: modify the clock signal frequency at each successive training iteration to a successively higher clock signal frequency until a determination that the performance of the clock signal does not fall within the target performance range; and in response to the determination that the performance of the clock signal does not fall within the target performance range, cause the application at the memory device, during the memory operation, of the highest clock signal frequency corresponding to the training iteration for which performance of the clock signal was within the target performance range. ### Claim 7 (depends on 1) The integrated circuit of claim 1, wherein the quality feedback message includes encoded data corresponding to a maximum voltage detected at the memory device based on the clock signal frequency. ### Claim 8 (depends on 7) The integrated circuit of claim 7, wherein the encoded data consists of n-bit binary data, the one or more processors to receive the n-bit binary data through n respective data (DQ) buses connected to the I/O interface. ### Claim 9 (depends on 7) The integrated circuit of claim 7, wherein the target performance range of the memory device corresponds to a minimum acceptable voltage level at the memory device based on the clock signal frequency. ### Claim 10 (depends on 1) The integrated circuit of claim 1, wherein the one or more processors are to determine the target performance range from serial presence detect (SPD) data corresponding to the memory device. ### Claim 11 (depends on 1) The integrated circuit of claim 1, wherein the one or more processors are at least one of: to determine whether the performance of the clock signal frequency falls within the target performance range of the memory device or to receive, through the I/O interface, information based on a determination as to whether the performance of the clock signal frequency falls within the target performance range of the memory device. ### Claim 12 (depends on 1) The integrated circuit of claim 1, wherein the I/O interface and the one or more processors are part of a memory controller, the integrated circuit further including a central processing unit connected to the memory controller through the I/O interface. ### Claim 13 (depends on 1) The integrated circuit of claim 1, wherein the one or more processors are to tune the target clock signal frequency during initialization of the memory device. ### Claim 14 A method to be performed at an integrated circuit of a memory subsystem, the method including: performing one or more training iterations to tune a target clock signal frequency to be applied at a memory device, each of the one or more training iterations including: causing a modified clock signal frequency to be applied at the memory device; and decoding a quality feedback message from the memory device including an indication of a performance of the clock signal frequency at the memory device; and in response to a determination that the performance of the clock signal frequency falls within a target performance range of the memory device and that the clock signal frequency is below the target clock signal frequency, performing a subsequent training iteration of the one or more training iterations, and otherwise causing application at the memory device, during a memory operation, of a highest clock signal frequency corresponding to a training iteration for which performance of the clock signal was within the target performance range. ### Claim 15 (depends on 14) The method of claim 14, wherein: the memory device is part of a memory module including a plurality of memory devices; performing includes performing the one or more training iterations to tune the target clock signal frequency to be applied at the memory devices; causing includes causing the modified clock signal frequency to be applied at the memory devices; and decoding a quality feedback message from the memory device includes decoding a respective quality feedback message from respective ones of the memory devices, each quality feedback message including an indication of a performance of the clock signal frequency at respective ones of the memory devices; and the method further includes, in response to a determination that the performance of the clock signal at said respective ones of the memory devices falls within a corresponding target performance range the respective ones of the memory devices, and that the clock signal frequency is below the target clock signal frequency, performing a subsequent training iteration of the one or more training iterations, and otherwise causing application at the memory devices, during memory operations, of a highest clock signal frequency corresponding to a training iteration for which performance of the clock signal was within target performance ranges of the memory devices. ### Claim 16 (depends on 15) The method of claim 15, wherein the memory module includes a dual inline memory module (DIMM), and the memory devices include respective dynamic random access memories (DRAMs). ### Claim 17 (depends on 15) The method of claim 15, wherein each of the one or more training iterations further includes modifying a termination level of at least one of the memory devices based on the clock signal frequency and prior to decoding. ### Claim 18 (depends on 14) The method of claim 14, wherein the one or more training iterations include a plurality of training iterations, the method including: modifying the clock signal frequency at each successive training iteration to a successively higher clock signal frequency until a determination that the performance of the clock signal does not fall within the target performance range; and in response to the determination that the performance of the clock signal does not fall within the target performance range, causing the application at the memory device, during the memory operation, of the highest clock signal frequency corresponding to the training iteration for which performance of the clock signal was within the target performance range. ### Claim 19 (depends on 14) The method of claim 14, wherein the quality feedback message includes encoded data corresponding to a maximum voltage detected at the memory device based on the clock signal frequency. ### Claim 20 (depends on 19) The method of claim 19, wherein the encoded data consists of n-bit binary data, the method including receiving the n-bit binary data through n respective data (DQ) buses connected to an I/O interface. ### Claim 21 A non-transitory machine-readable storage medium having instructions stored thereon, the instructions, when executed by an integrated circuit of a memory subsystem, to cause the integrated circuit to perform operations including: performing one or more training iterations to tune a target clock signal frequency to be applied at a memory device, each of the one or more training iterations including: causing a modified clock signal frequency to be applied at the memory device; and decoding a quality feedback message from the memory device including an indication of a performance of the clock signal frequency at the memory device; and in response to a determination that the performance of the clock signal frequency falls within a target performance range of the memory device and that the clock signal frequency is below the target clock signal frequency, performing a subsequent training iteration of the one or more training iterations, and otherwise causing application at the memory device, during a memory operation, of a highest clock signal frequency corresponding to a training iteration for which performance of the clock signal was within the target performance range. ### Claim 22 (depends on 21) The machine-readable storage medium of claim 21, wherein: the memory device is part of a memory module including a plurality of memory devices; performing includes performing the one or more training iterations to tune the target clock signal frequency to be applied at the memory devices; causing includes causing the modified clock signal frequency to be applied at the memory devices; and decoding a quality feedback message from the memory device includes decoding a respective quality feedback message from respective ones of the memory devices, each quality feedback message including an indication of a performance of the clock signal frequency at respective ones of the memory devices; and the operations further include, in response to a determination that the performance of the clock signal at said respective ones of the memory devices falls within a corresponding target performance range the respective ones of the memory devices, and that the clock signal frequency is below the target clock signal frequency, performing a subsequent training iteration of the one or more training iterations, and otherwise causing application at the memory devices, during memory operations, of a highest clock signal frequency corresponding to a training iteration for which performance of the clock signal was within target performance ranges of the memory devices. ### Claim 23 (depends on 22) The machine-readable storage medium of claim 22, wherein the memory module includes a dual inline memory module (DIMM), and the memory devices include respective dynamic random access memories (DRAMs). ### Claim 24 (depends on 23) The machine-readable storage medium of claim 23, wherein the DIMM includes a register coupled to the DRAMs, the operations including causing the modified clock signal frequency to be applied by sending a command through the register to modify clock signal frequency at the DRAMs. ### Claim 25 (depends on 21) The machine-readable storage medium of claim 21, wherein the one or more training iterations include a plurality of training iterations, the operations including: modifying the clock signal frequency at each successive training iteration to a successively higher clock signal frequency until a determination that the performance of the clock signal does not fall within the target performance range; and in response to the determination that the performance of the clock signal does not fall within the target performance range, causing the application at the memory device, during the memory operation, of the highest clock signal frequency corresponding to the training iteration for which performance of the clock signal was within the target performance range.