# US 12,217,784 B2 · Boosted writeback voltage > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,217,784 B2 - Document ID: US12217784B2 - Status: Granted - Kind: B2 - Application number: 17/909,940 - Filed: 2021-03-08 - Published: 2024-06-20 - Granted: 2025-02-04 - Earliest claimed: 2020-03-19 - Assignees: Rambus Inc. - Applicants: Rambus Inc. - Inventors: Thomas Vogelsang; Brent S. Haukness - Web page: https://patentgrep.com/patent/US12217784B2 ## CPC - G11C 11/40611: {External triggering or timing of internal or partially internal refresh operations, e.g. auto-refresh or CAS-before-RAS triggered refresh} - G11C 7/065: {Differential amplifiers of latching type} - G11C 7/08: Control thereof - G11C 11/40626: {Temperature related aspects of refresh operations} - G11C 11/4091: Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating - G11C 11/4094: Bit-line management or control circuits - G11C 5/025: {Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device (geometrical lay-out of the components in integrated circuits, geometrical lay-out of the components in integrated circuits H10D89/10)} - G11C 11/4074: Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits - Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management - G11C: STATIC STORES (semiconductor memory devices H10B) - Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE ## Abstract The dynamic memory array of a DRAM device is operated using at least two voltages. The first voltage, which is used to power the sense amplifiers during sense (i.e., read) operations and most other column operations (e.g., precharge, activate, write), is the operating (i.e., switching) voltage of a majority of the digital logic circuitry of the DRAM device. The second voltage, which determines the voltage written to the capacitor of the DRAM cells (i.e., bitline voltage) is greater than the operating (i.e., switching) voltage of a majority of the digital logic circuitry of the DRAM device. The digital logic circuitry is operated using a supply voltage that is lower than the voltage written to the capacitors of the DRAM array. This allows lower voltage swing digital logic to be used for a majority of the logic on the DRAM device while writing a larger voltage to the DRAM cells. ## Claims ### Claim 1 A dynamic random access memory (DRAM) device, comprising: digital logic circuitry to at least process column addresses and row addresses to retrieve data stored in a dynamic memory array, the digital logic circuitry to operate using a first digital logic supply voltage level; and, sense amplifier circuits that are part of the dynamic memory array to operate using the first digital logic supply voltage level during column operations and sense operations until a pair of cross-coupled inverters of the sense amplifier circuits reach a stable state using the first digital logic supply voltage and to operate, during writeback operations after the pair of cross-coupled inverters reach the stable state using the first digital logic supply voltage, using a boosted bitline voltage that is greater than the first digital logic supply voltage level. ### Claim 2 (depends on 1) The DRAM device of claim 1, wherein the digital logic circuitry is implemented using a high-k metal gate process. ### Claim 3 (depends on 1) The DRAM device of claim 1, wherein the pair of cross-coupled inverters are in a bi-stable flip-flop configuration coupled to respective bitlines of the dynamic memory array, the pair of cross-coupled inverters each having a negative supply node and a positive supply node. ### Claim 4 (depends on 3) The DRAM device of claim 3, wherein the boosted bitline voltage is selectively coupled to the positive supply node of the pair of cross-coupled inverters during writeback operations. ### Claim 5 (depends on 4) The DRAM device of claim 4, wherein the first digital logic supply voltage level is selectively coupled to the positive supply node of the pair of cross-coupled inverters during sense operations and column operations. ### Claim 6 (depends on 4) The DRAM device of claim 4, wherein the boosted bitline voltage is selectively coupled to the positive supply node of the pair of cross-coupled inverters during refresh operations. ### Claim 7 (depends on 4) The DRAM device of claim 4, wherein the boosted bitline voltage is selectively coupled to the positive supply node of the pair of cross-coupled inverters using a p-channel field effect transistor (PFET) having a PFET gate node to be controlled using logic that applies voltages to the PFET gate node that at least reach the boosted bitline voltage minus a threshold voltage of the PFET. ### Claim 8 A dynamic random access memory (DRAM) device, comprising: sense amplifier circuits that are part of a dynamic memory array to operate using a first digital logic supply voltage level during a first plurality of column operations and a first plurality of sense operations that lasts at least until a pair of cross-coupled inverters of the sense amplifier circuits reach a stable state using the first digital logic supply voltage, and to operate, during a first plurality of writeback operations that occur after respective ones of the first plurality of sense operations to writeback data sensed by the respective ones of the first plurality of sense operations, using a first bitline voltage that is greater than the first digital logic supply voltage level; and, digital logic to at least process received commands, column addresses, and row addresses to retrieve data stored in the dynamic memory array, the digital logic to operate using the first digital logic supply voltage level. ### Claim 9 (depends on 8) The DRAM of claim 8, wherein the first bitline voltage is based on a first received command. ### Claim 10 (depends on 9) The DRAM of claim 9, wherein the sense amplifier circuits are to, based on a second received command, and during a writeback operation that occurs after a sense operation to writeback data sensed by the sense operation, operate using a second bitline voltage that is equal to the first digital logic supply voltage level. ### Claim 11 (depends on 9) The DRAM of claim 9, wherein the sense amplifier circuits are to, based on a second received command, and during a writeback operation that occurs after a sense operation to writeback data sensed by the sense operation, operate using a second bitline voltage that is not equal to the first bitline voltage and is greater than or equal to the first digital logic supply voltage level. ### Claim 12 (depends on 10) The DRAM of claim 10, wherein the second bitline voltage is based on a temperature of the DRAM. ### Claim 13 (depends on 8) The DRAM of claim 8, wherein the sense amplifier circuits are to, based on a first received command, precharge respective bitlines of the dynamic memory array to a precharge voltage that is derived from the first digital logic supply voltage level. ### Claim 14 (depends on 8) The DRAM of claim 8, wherein the sense amplifier circuits are to, based on a first received command, perform refresh operations using a second bitline voltage that is equal to the first digital logic supply voltage level. ### Claim 15 A memory controller, comprising: a command interface to communicate a first indicator and a second indicator to a memory device, based at least on the first indicator, the memory device to operate a plurality of sense amplifier circuits that are part of a dynamic memory array of the memory device using a first digital logic supply voltage level during a first column operation and a first sense operation that lasts at least until cross-coupled inverters of the plurality of sense amplifier circuits reach stable states using the first digital logic supply voltage, and to operate, during a first writeback operation that occurs after the first sense operation reaches the stable states using the first digital logic supply voltage to writeback data sensed by the first sense operation, using a first bitline voltage that is greater than the first digital logic supply voltage level, the memory device to, based at least on the second indicator, to operate, during a second writeback operation that occurs after a second sense operation reaches the stable states using the first digital logic supply voltage to writeback data sensed by the second sense operation, using a second bitline voltage that is equal to the first digital logic supply voltage level; and, a data interface to receive data sensed by the respective ones of the first plurality of sense operations. ### Claim 16 (depends on 15) The memory controller of claim 15, wherein the first indicator is based on a command. ### Claim 17 (depends on 15) The memory controller of claim 15, wherein the command interface is to communicate a third indicator to the memory device, the memory device to, based on the third indicator, and during a third writeback operation that occurs after a third sense operation reaches the stable states using the first digital logic supply voltage, operate the plurality of sense amplifier circuits using a third bitline voltage that is not equal to the first bitline voltage and is greater than or equal to the first digital logic supply voltage level to writeback data sensed by the third sense operation. ### Claim 18 (depends on 15) The memory controller of claim 15, wherein the third indicator is based on a command. ### Claim 19 (depends on 15) The memory controller of claim 15, wherein the first bitline voltage is based on a temperature of the memory device. ### Claim 20 (depends on 17) The memory controller of claim 17, wherein the third bitline voltage is based on a temperature of the memory device.