# US 12,217,717 B2 · Circuit and method for conditioning clock signal, display panel, and display device

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- Number: US 12,217,717 B2
- Document ID: US12217717B2
- Status: Granted
- Kind: B2
- Application number: 17/756,663
- Filed: 2022-04-19
- Published: 2024-05-16
- Granted: 2025-02-04
- Earliest claimed: 2022-03-24
- Assignees: Tcl China Star Optoelectronics Technology Co., Ltd.
- Applicants: Tcl China Star Optoelectronics Technology Co., Ltd.
- Inventors: Zhaoxian Zhong
- Web page: https://patentgrep.com/patent/US12217717B2

## CPC

- G09G 3/20: for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix {no fixed position being assigned to or needed to be assigned to the individual characters or partial characters}
- G09G 3/3677: {suitable for active matrices only}
- G09G 3/3266: Details of drivers for scan electrodes
- G09G 3/3648: {using an active matrix (G09G3/367 - G09G3/3696 take precedence)}
- G09G 2310/08: Details of timing specific for flat panels, other than clock recovery
- Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management
- G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00)
- Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE

## Abstract

The present disclosure relates to a circuit and a method for conditioning a clock signal, display panel, and display device. The circuit includes a signal conversion circuit and a delay processing circuit; when a voltage amplitude of the converted electrical signal falls within a turn-on threshold range, the delay processing circuit receives the N-th clock signal transmitted from the N-th clock signal output terminal, and performs delay processing on the N-th clock signal, so as to avoid occurrence of GOA-stage transfer abnormality when one of the plurality of CK clock signals is in an abnormal condition that no signal is output.

## Claims

### Claim 1

A clock signal conditioning circuit comprising:
a signal conversion circuit, wherein an input terminal of the signal conversion circuit is configured to be connected to a (N+1)-th clock signal output terminal, an output terminal of the signal conversion circuit is configured to output a converted electrical signal, and the (N+1)-th clock signal output terminal is configured to be connected to the (N+1)-th stage GOA drive circuit; and a delay processing circuit configured to receive the converted electrical signal transmitted from the signal conversion circuit; wherein the delay processing circuit is further configured to receive an N-th clock signal transmitted from the N-th clock signal output terminal when a voltage amplitude of the converted electrical signal falls within a turn-on threshold range, perform delay processing on the N-th clock signal based on a preset interval clock signal, to obtain a delayed clock signal, and transmit the delayed clock signal to the (N+1)-th stage GOA drive circuit; and a timing of the delayed clock signal is the same as a timing of the (N+1)-th clock signal output from the (N+1)-th clock signal output terminal,
wherein the delay processing circuit comprises:
a switch circuit, wherein a control terminal of the switch circuit is configured to receive the converted electrical signal, and an input terminal of the switch circuit is configured to be connected to the N-th clock signal output terminal; and
a delay circuit, wherein a first input terminal of the delay circuit is connected to the output terminal of the switch circuit, a second input terminal of the delay circuit is configured to receive a preset interval clock signal; the output terminal of the delay circuit is configured to be connected to the (N+1)-th stage GOA drive circuit, and
wherein when no signal is output from the (N+1)-th clock signal output terminal, the voltage amplitude of the converted electrical signal falls within the turn-on threshold range of the switch circuit.

### Claim 2 (depends on 1)

The clock signal conditioning circuit according to claim 1, wherein the signal conversion circuit comprises a Schmitt trigger; and
an input terminal of the Schmitt trigger is connected to the (N+1)-th clock signal output terminal, and an output terminal of the Schmitt trigger is connected to the control terminal of the switch circuit.

### Claim 3 (depends on 2)

The clock signal conditioning circuit according to claim 2, wherein the switch circuit comprises a PMOS transistor; and
a gate of the PMOS transistor is connected to the output terminal of the Schmitt trigger, a source of the PMOS transistor is connected to the N-th clock signal output terminal, and a drain of the PMOS transistor is connected to the first input terminal of the delay circuit.

### Claim 4 (depends on 3)

The clock signal conditioning circuit according to claim 3, wherein the delay circuit comprises a first D flip-flop, a second D flip-flop, a third D flip-flop, a fourth D flip-flop, a fifth D flip-flop, a first AND gate, a second AND gate, a third AND gate, and a fourth AND gate;
an input terminal of the first D flip-flop is connected to the drain of the PMOS transistor, an output terminal of the first D flip-flop is connected to an input terminal of the second D flip-flop, an output terminal of the second D flip-flop is connected to an input terminal of the third D flip-flop, an output terminal of the third D flip-flop is connected to an input terminal of the fourth D flip-flop, and an output terminal of the fourth D flip-flop is connected to an input terminal of the fifth D flip-flop;
a clock terminal of the first D flip-flop, a clock terminal of the second D flip-flop, a clock terminal of the third D flip-flop, a clock terminal of the fourth D flip-flop, and a clock terminal of the fifth D flip-flop are respectively configured to receive the interval clock signal; and
a first input terminal of the first AND gate is connected to the output terminal of the first D flip-flop, a second input terminal of the first AND gate is connected to the output terminal of the second D flip-flop, and an output terminal of the first AND gate is connected to a first input terminal of the third AND gate; a first input terminal of the second AND gate is connected to the output terminal of the third D flip-flop, a second input terminal of the second AND gate is connected to the output terminal of the fourth D flip-flop, and an output terminal of the second AND gate is connected to a second input terminal of the third AND gate; a first input terminal of the fourth AND gate is connected to an output terminal of the third AND gate, a second input terminal of the fourth AND gate is connected to an output terminal of the fifth D flip-flop, and an output terminal of the fourth AND gate is connected to the (N+1)-th stage GOA drive circuit.

### Claim 5 (depends on 1)

The clock signal conditioning circuit according to claim 1, further comprising a clock signal generator; wherein the clock signal generator comprises an interval clock output terminal and a plurality of clock signal output terminals; and
the interval clock output terminal is configured to output the preset interval clock signal.

### Claim 6

A display panel comprising a pixel unit, a GOA circuit, and a clock signal conditioning circuit; wherein the clock signal conditioning circuit is connected to the GOA circuit, and the GOA circuit is connected to the pixel unit; and
wherein the clock signal conditioning circuit comprises:
a signal conversion circuit, wherein an input terminal of the signal conversion circuit is configured to be connected to a (N+1)-th clock signal output terminal, an output terminal of the signal conversion circuit is configured to output a converted electrical signal, and the (N+1)-th clock signal output terminal is configured to be connected to the (N+1)-th stage GOA drive circuit; and
a delay processing circuit configured to receive the converted electrical signal transmitted from the signal conversion circuit; wherein the delay processing circuit is further configured to receive an N-th clock signal transmitted from the N-th clock signal output terminal when a voltage amplitude of the converted electrical signal falls within a turn-on threshold range, perform delay processing on the N-th clock signal based on a preset interval clock signal, to obtain a delayed clock signal, and transmit the delayed clock signal to the (N+1)-th stage GOA drive circuit; and a timing of the delayed clock signal is the same as a timing of the (N+1)-th clock signal output from the (N+1)-th clock signal output terminal,
wherein the delay processing circuit comprises:
a switch circuit, wherein a control terminal of the switch circuit is configured to receive the converted electrical signal, and an input terminal of the switch circuit is configured to be connected to the N-th clock signal output terminal; and
a delay circuit, wherein a first input terminal of the delay circuit is connected to the output terminal of the switch circuit, a second input terminal of the delay circuit is configured to receive a preset interval clock signal; the output terminal of the delay circuit is configured to be connected to the (N+1)-th stage GOA drive circuit, and
wherein when no signal is output from the (N+1)-th clock signal output terminal, the voltage amplitude of the converted electrical signal falls within the turn-on threshold range of the switch circuit.

### Claim 7 (depends on 6)

The display panel according to claim 6, wherein the signal conversion circuit comprises a Schmitt trigger; and
an input terminal of the Schmitt trigger is connected to the (N+1)-th clock signal output terminal, and an output terminal of the Schmitt trigger is connected to the control terminal of the switch circuit.

### Claim 8 (depends on 7)

The display panel according to claim 7, wherein the switch circuit comprises a PMOS transistor; and
a gate of the PMOS transistor is connected to the output terminal of the Schmitt trigger, a source of the PMOS transistor is connected to the N-th clock signal output terminal, and a drain of the PMOS transistor is connected to the first input terminal of the delay circuit.

### Claim 9 (depends on 8)

The display panel according to claim 8, wherein the delay circuit comprises a first D flip-flop, a second D flip-flop, a third D flip-flop, a fourth D flip-flop, a fifth D flip-flop, a first AND gate, a second AND gate, a third AND gate, and a fourth AND gate;
an input terminal of the first D flip-flop is connected to the drain of the PMOS transistor, an output terminal of the first D flip-flop is connected to an input terminal of the second D flip-flop, an output terminal of the second D flip-flop is connected to an input terminal of the third D flip-flop, an output terminal of the third D flip-flop is connected to an input terminal of the fourth D flip-flop, and an output terminal of the fourth D flip-flop is connected to an input terminal of the fifth D flip-flop;
a clock terminal of the first D flip-flop, a clock terminal of the second D flip-flop, a clock terminal of the third D flip-flop, a clock terminal of the fourth D flip-flop, and a clock terminal of the fifth D flip-flop are respectively configured to receive the interval clock signal; and
a first input terminal of the first AND gate is connected to the output terminal of the first D flip-flop, a second input terminal of the first AND gate is connected to the output terminal of the second D flip-flop, and an output terminal of the first AND gate is connected to a first input terminal of the third AND gate; a first input terminal of the second AND gate is connected to the output terminal of the third D flip-flop, a second input terminal of the second AND gate is connected to the output terminal of the fourth D flip-flop, and an output terminal of the second AND gate is connected to a second input terminal of the third AND gate; a first input terminal of the fourth AND gate is connected to an output terminal of the third AND gate, a second input terminal of the fourth AND gate is connected to an output terminal of the fifth D flip-flop, and an output terminal of the fourth AND gate is connected to the (N+1)-th stage GOA drive circuit.

### Claim 10 (depends on 6)

The display panel according to claim 6, further comprising a clock signal generator; wherein the clock signal generator comprises an interval clock output terminal and a plurality of clock signal output terminals; and
the interval clock output terminal is configured to output the preset interval clock signal.

### Claim 11

A display device comprising a display panel;
the display panel comprises a pixel unit, a GOA circuit, and a clock signal conditioning circuit; the clock signal conditioning circuit is connected to the GOA circuit, and the GOA circuit is connected to the pixel unit; and
wherein the clock signal conditioning circuit comprises:
a signal conversion circuit, wherein an input terminal of the signal conversion circuit is configured to be connected to a (N+1)-th clock signal output terminal, an output terminal of the signal conversion circuit is configured to output a converted electrical signal, and the (N+1)-th clock signal output terminal is configured to be connected to the (N+1)-th stage GOA drive circuit; and
a delay processing circuit configured to receive the converted electrical signal transmitted from the signal conversion circuit; wherein the delay processing circuit is further configured to receive an N-th clock signal transmitted from the N-th clock signal output terminal when a voltage amplitude of the converted electrical signal falls within a turn-on threshold range, perform delay processing on the N-th clock signal based on a preset interval clock signal, to obtain a delayed clock signal, and transmit the delayed clock signal to the (N+1)-th stage GOA drive circuit; and a timing of the delayed clock signal is the same as a timing of the (N+1)-th clock signal output from the (N+1)-th clock signal output terminal,
wherein the delay processing circuit comprises:
a switch circuit, wherein a control terminal of the switch circuit is configured to receive the converted electrical signal, and an input terminal of the switch circuit is configured to be connected to the N-th clock signal output terminal; and
a delay circuit, wherein a first input terminal of the delay circuit is connected to the output terminal of the switch circuit, a second input terminal of the delay circuit is configured to receive a preset interval clock signal; the output terminal of the delay circuit is configured to be connected to the (N+1)-th stage GOA drive circuit, and
wherein when no signal is output from the (N+1)-th clock signal output terminal, the voltage amplitude of the converted electrical signal falls within the turn-on threshold range of the switch circuit.

### Claim 12 (depends on 11)

The display device according to claim 11, wherein the signal conversion circuit comprises a Schmitt trigger; and
an input terminal of the Schmitt trigger is connected to the (N+1)-th clock signal output terminal, and an output terminal of the Schmitt trigger is connected to the control terminal of the switch circuit.

### Claim 13 (depends on 12)

The display device according to claim 12, wherein the switch circuit comprises a PMOS transistor; and
a gate of the PMOS transistor is connected to the output terminal of the Schmitt trigger, a source of the PMOS transistor is connected to the N-th clock signal output terminal, and a drain of the PMOS transistor is connected to the first input terminal of the delay circuit.

### Claim 14 (depends on 13)

The display device according to claim 13, wherein the delay circuit comprises a first D flip-flop, a second D flip-flop, a third D flip-flop, a fourth D flip-flop, a fifth D flip-flop, a first AND gate, a second AND gate, a third AND gate, and a fourth AND gate;
an input terminal of the first D flip-flop is connected to the drain of the PMOS transistor, an output terminal of the first D flip-flop is connected to an input terminal of the second D flip-flop, an output terminal of the second D flip-flop is connected to an input terminal of the third D flip-flop, an output terminal of the third D flip-flop is connected to an input terminal of the fourth D flip-flop, and an output terminal of the fourth D flip-flop is connected to an input terminal of the fifth D flip-flop;
a clock terminal of the first D flip-flop, a clock terminal of the second D flip-flop, a clock terminal of the third D flip-flop, a clock terminal of the fourth D flip-flop, and a clock terminal of the fifth D flip-flop are respectively configured to receive the interval clock signal; and
a first input terminal of the first AND gate is connected to the output terminal of the first D flip-flop, a second input terminal of the first AND gate is connected to the output terminal of the second D flip-flop, and an output terminal of the first AND gate is connected to a first input terminal of the third AND gate; a first input terminal of the second AND gate is connected to the output terminal of the third D flip-flop, a second input terminal of the second AND gate is connected to the output terminal of the fourth D flip-flop, and an output terminal of the second AND gate is connected to a second input terminal of the third AND gate; a first input terminal of the fourth AND gate is connected to an output terminal of the third AND gate, a second input terminal of the fourth AND gate is connected to an output terminal of the fifth D flip-flop, and an output terminal of the fourth AND gate is connected to the (N+1)-th stage GOA drive circuit.

### Claim 15 (depends on 11)

The display device according to claim 11, further comprising a clock signal generator; wherein the clock signal generator comprises an interval clock output terminal and a plurality of clock signal output terminals; and
the interval clock output terminal is configured to output the preset interval clock signal.