# US 12,217,700 B2 · Display apparatus

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 12,217,700 B2
- Document ID: US12217700B2
- Status: Granted
- Kind: B2
- Application number: 18/513,705
- Filed: 2023-11-20
- Published: 2024-03-21
- Granted: 2025-02-04
- Earliest claimed: 2020-12-24
- Assignees: LG Display Co., Ltd.
- Applicants: LG Display Co., Ltd.
- Inventors: Donghyun Kim; Dongjun Kim
- Web page: https://patentgrep.com/patent/US12217700B2

## CPC

- G09G 3/20: for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix {no fixed position being assigned to or needed to be assigned to the individual characters or partial characters}
- G09G 3/3266: Details of drivers for scan electrodes
- G09G 2300/0408: Integration of the drivers onto the display substrate
- G09G 2300/0417: Special arrangements specific to the use of low carrier mobility technology
- G09G 2310/0267: Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
- G09G 2310/0286: Details of a shift registers arranged for use in a driving circuit
- G09G 2310/0289: Details of voltage level shifters arranged for use in a driving circuit
- G09G 2310/08: Details of timing specific for flat panels, other than clock recovery
- G09G 2320/0214: with crosstalk due to leakage current of pixel switch in active matrix panels
- G09G 2320/041: Temperature compensation
- G09G 2340/0435: Change or adaptation of the frame rate of the video stream
- G11C 19/28: using semiconductor elements (G11C19/14, G11C19/36 take precedence)
- G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00)
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

A display apparatus includes an active area, an inactive area surrounding the active area, a pixel disposed in the active area, and a driver IC, a gate driver, a low-potential power supply line, a high-potential power supply line and a subframe controller disposed in the inactive area, wherein the subframe controller is disposed between the pixel and the gate driver.

## Claims

### Claim 1

A display apparatus, comprising:
a substrate;
a driver IC disposed on a side of the substrate; and
a gate driver disposed on a side of the substrate;
a pad for low-potential power disposed on a left side and a right side of the driver IC; and
a pad for high-potential power disposed on the left side and the right side of the driver IC,
wherein the gate driver includes:
a transistor T1 including a gate electrode electrically connected to a node Q and a capacitor CQ, and electrically connected between an input terminal of a gate low voltage and an output node;
a transistor T2 including a gate electrode electrically connected to a node QB and electrically connected between an input terminal of a gate high voltage and the output node;
a capacitor CB electrically connected between the input terminal of the gate high voltage and the gate electrode of the transistor T2;
a transistor T3 including a gate electrode electrically connected to an input terminal of a clock signal, and electrically connected between an input terminal of a start signal and the node Q;
a transistor T4 electrically connected the input terminal of the gate high voltage;
a transistor T5 electrically connected between the input terminal of the clock signal and the transistor T2;
a transistor T6 electrically connected between the input terminal of the gate high voltage and the transistor T2; and
a transistor TA electrically connected between the transistor T3 and the transistor T1.

### Claim 2 (depends on 1)

The display apparatus according to claim 1, further comprising:
a low potential power line disposed on the left side and the right side of the driver IC; and
a high potential power line disposed on the left side and the right side of the driver IC and a lower side of the driver IC.

### Claim 3 (depends on 2)

The display apparatus according to claim 2, wherein the high potential power line is disposed closer to the driver IC than the low potential power line on the left and right sides of the driver IC, respectively.

### Claim 4 (depends on 1)

The display apparatus according to claim 1, wherein the clock signal is applied to the gate electrode of the transistor T2, and
wherein the start signal is applied to the gate electrode of the transistor T1.

### Claim 5 (depends on 1)

The display apparatus according to claim 1, wherein the transistor T4 is connected between the input terminal of the gate high voltage and the input terminal of the clock signal.

### Claim 6 (depends on 1)

The display apparatus according to claim 1, wherein the gate driver includes:
a Q2 controller including the transistor T3 and activating a node Q2 in response to the clock signal;
a QB controller activating the node QB as opposed to the node Q2 in response to the clock signal and including the transistor T5, the transistor T4, the transistor T6 and the capacitor CB;
an output unit including the transistor T1 serving as a pull-down element, the transistor T2 serving as a pull-up element and the capacitor CQ; and
a stabilization unit including the transistor TA and blocking an electrical connection between the node Q2 and the node Q when the node Q is bootstrapped.

### Claim 7 (depends on 1)

The display apparatus according to claim 1, wherein a first electrode of the transistor T3 is connected to the input terminal of the start signal,
wherein a second electrode of the transistor T3 is connected to a first electrode of the transistor TA, and
wherein a second electrode of the transistor TA is connected to the gate electrode of the transistor T1.

### Claim 8 (depends on 1)

The display apparatus according to claim 1, wherein the gate driver includes an oxide transistor.

### Claim 9 (depends on 1)

The display apparatus according to claim 1, further comprising: a pixel circuit including an oxide transistor on the substrate.

### Claim 10 (depends on 1)

The display apparatus according to claim 1, wherein the gate driver is driven at a scanning rate of less than 60 Hz.

### Claim 11 (depends on 1)

The display apparatus according to claim 1, further comprising:
a pixel disposed in an active area on the substrate; and
a subframe controller disposed on a side of the substrate,
wherein the subframe controller is disposed between the pixel and the gate driver,
wherein the driver IC includes a gate low voltage pad connected to the gate driver, and
wherein the gate low voltage pad is connected to a source electrode of the subframe controller.

### Claim 12 (depends on 11)

The display apparatus according to claim 11, wherein the driver IC includes:
a subframe control pad connected to a gate electrode of the subframe controller; and
a clock signal pad, a start signal pad and a gate high voltage pad connected to the gate driver.

### Claim 13 (depends on 11)

The display apparatus according to claim 11, wherein the driver IC includes a gate high voltage pad connected to the gate driver.

### Claim 14 (depends on 11)

The display apparatus according to claim 11, wherein a drain electrode of the subframe controller is electrically connected to an output terminal of the gate driver, and the output terminal of the gate driver is connected to the pixel.

### Claim 15 (depends on 11)

The display apparatus according to claim 11, wherein the subframe controller is in a turn-off state during a main frame period of the pixel and is in a turn-on state during a subframe period of the pixel.

### Claim 16 (depends on 15)

The display apparatus according to claim 15, wherein a drain electrode of the subframe controller outputs an output voltage of −9 V when the subframe controller is in the turn-on state.

### Claim 17 (depends on 11)

The display apparatus according to claim 11, wherein a drain electrode of the subframe controller is connected to a line extended from the gate driver to the pixel.