# US 12,217,660 B2 · Display device and driving method thereof > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,217,660 B2 - Document ID: US12217660B2 - Status: Granted - Kind: B2 - Application number: 18/368,909 - Filed: 2023-09-15 - Published: 2024-01-04 - Granted: 2025-02-04 - Earliest claimed: 2021-12-03 - Assignees: Samsung Display Co., Ltd. - Applicants: Samsung Display Co., Ltd. - Inventors: Soon-Dong Kim; Sangan Kwon; Taehoon Kim; Jin-Wook Yang - Web page: https://patentgrep.com/patent/US12217660B2 ## CPC - G09G 3/32: semiconductive, e.g. using light-emitting diodes [LED] - G09G 3/3233: with pixel circuitry controlling the current through the light-emitting element - G09G 2300/0819: used for counteracting undesired variations, e.g. feedback or autozeroing - G09G 2300/0842: forming a memory circuit, e.g. a dynamic memory with one capacitor - G09G 2300/0861: with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes - G09G 2310/0251: Precharge or discharge of pixel before applying new pixel voltage - G09G 2310/0262: The addressing of the pixel, in a display other than an active matrix LCD, involving the control of two or more scan electrodes or two or more data electrodes, e.g. pixel voltage dependent on signals of two data electrodes - G09G 2310/0267: Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays - G09G 2310/0286: Details of a shift registers arranged for use in a driving circuit - G09G 2310/04: Partial updating of the display screen - G09G 2330/021: Power management, e.g. power saving - G09G 2340/0435: Change or adaptation of the frame rate of the video stream - G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00) ## Abstract A display device includes: a display panel including a plurality of pixels connected to a plurality of scan lines; a scan driving circuit, which drives the plurality of scan lines in synchronization with a clock signal; and a driving controller, which outputs the clock signal. While an operating mode is a multi-frequency mode, the driving controller comparts the display panel into a first display area and a second display area. A hold frame of the multi-frequency mode includes a first section during which the first display area is driven, and a second section during which the second display area is driven. The driving controller outputs the clock signal of a normal power mode during the first section and outputs the clock signal of a low-power mode during the second section. ## Claims ### Claim 1 A display device comprising: a display panel including a plurality of pixels connected to a plurality of scan lines and divided into a first display area which operates at a first operating frequency and a second display area which operates at a second operating frequency; a scan driving circuit, which drives the plurality of scan lines in synchronization with a clock signal; and a driving controller, which outputs the clock signal, wherein, while an operating mode is a multi-frequency mode, the scan driving circuit provides scan signals of a first operating frequency to first scan lines positioned in the first display area among the plurality of scan lines, and provides scan signals of a second operating frequency lower than the first operating frequency to second scan lines positioned in the second display area among the plurality of scan lines, wherein a hold frame of the multi-frequency mode includes a first section during which the first display area is driven, and a second section during which the second display area is driven, and wherein the driving controller has a control signal generator that outputs the clock signal in a normal power mode during the first section and outputs the clock signal in a low-power mode during the second section. ### Claim 2 (depends on 1) The display device of claim 1, wherein, during the first section, a frequency of the clock signal is a first clock frequency, and wherein, during the second section, the frequency of the clock signal is a second clock frequency lower than the first clock frequency. ### Claim 3 (depends on 2) The display device of claim 2, wherein, during the first section, the clock signal has a first pulse width, and wherein, during the second section, the clock signal has a second pulse width greater than the first pulse width. ### Claim 4 (depends on 2) The display device of claim 2, wherein the driving controller receives a mode signal and outputs the clock signal having one of the first clock frequency and the second clock frequency in response to the mode signal. ### Claim 5 (depends on 1) The display device of claim 1, further comprising: a voltage generator, which generates a first voltage and a second voltage in response to a voltage control signal, wherein the driving controller outputs the voltage control signal corresponding to the operating mode and outputs the clock signal that swings between the first voltage and the second voltage. ### Claim 6 (depends on 5) The display device of claim 5, wherein, while the operating mode is a single-frequency mode, the first voltage has a first voltage level, and the second voltage has a second voltage level lower than the first voltage level. ### Claim 7 (depends on 6) The display device of claim 6, wherein, while the operating mode is the multi-frequency mode, during the second section, the first voltage has a third voltage level lower than the first voltage level, and the second voltage has a fourth voltage level higher than the second voltage level. ### Claim 8 (depends on 1) The display device of claim 1, wherein, during the first section of the hold frame, the clock signal has a first amplitude, and Wherein, during the second section of the hold frame, the clock signal has a second amplitude smaller than the first amplitude. ### Claim 9 (depends on 1) The display device of claim 1, wherein, while the operating mode is the multi-frequency mode, the driving controller outputs a scan-enable signal indicating a start timing of the second section, and wherein the scan driving circuit maintains scan signals, which are provided to the second scan lines positioned in the second display area, from among the plurality of scan lines at inactive levels in response to the scan-enable signal. ### Claim 10 (depends on 1) The display device of claim 1, wherein, during the first section of the hold frame, the clock signal has a first pulse width and a first amplitude, and wherein, during the second section of the hold frame, the clock signal has a second pulse width greater than the first pulse width and a second amplitude smaller than the first amplitude. ### Claim 11 (depends on 1) The display device of claim 1, wherein, while the operating mode is a single-frequency mode, the scan driving circuit provides the plurality of scan lines with scan signals of a normal frequency lower than or equal to the first operating frequency and higher than the second operating frequency. ### Claim 12 A display device comprising: a display panel including a plurality of pixels connected to a plurality of scan lines and divided into a first display area which operates at a first operating frequency and a second display area which operates at a second operating frequency; a scan driving circuit, which drives the plurality of scan lines in synchronization with a clock signal; a voltage generator, which generates a first voltage and a second voltage in response to a voltage control signal; and a driving controller, which outputs the clock signal, wherein, in a multi-frequency mode, the scan driving circuit provides scan signals of a first operating frequency to first scan lines positioned in the first display area among the plurality of scan lines, and provides scan signals of a second operating frequency lower than the first operating frequency to second scan lines positioned in the second display area among the plurality of scan lines, wherein a hold frame of the multi-frequency mode includes a first section during which the first display area is driven, and a second section during which the second display area is driven, wherein a voltage difference between the first voltage and the second voltage during the second section is smaller than a voltage difference between the first voltage and the second voltage during the first section, and wherein the clock signal is a signal that swings between the first voltage and the second voltage. ### Claim 13 (depends on 12) The display device of claim 12, wherein, during the first section, the first voltage has a first voltage level, and the second voltage has a second voltage level different from the first voltage level. ### Claim 14 (depends on 13) The display device of claim 13, wherein, during the second section, the first voltage has a third voltage level lower than the first voltage level, and the second voltage has a fourth voltage level higher than the second voltage level. ### Claim 15 (depends on 12) The display device of claim 12, wherein, during the first section, the clock signal has a first clock frequency, and wherein, during the second section, the clock signal has a second clock frequency lower than the first clock frequency. ### Claim 16 (depends on 15) The display device of claim 15, wherein, during the first section, the clock signal has a first pulse width, and Wherein, during the second section, the clock signal has a second pulse width greater than the first pulse width. ### Claim 17 An electronic device comprising: a display device, which receives a mode signal from a host processor and displays an image, wherein the display device comprises: a display panel including a plurality of pixels connected to a plurality of scan lines and divided into a first display area which operates at a first operating frequency and a second display area which operates at a second operating frequency; a scan driving circuit, which drives the plurality of scan lines in synchronization with a clock signal; and a driving controller, which outputs the clock signal in response to the mode signal, wherein, while an operating mode is a multi-frequency mode, the scan driving circuit provides scan signals of a first operating frequency to first scan lines positioned in the first display area among the plurality of scan lines, and provides scan signals of a second operating frequency lower than the first operating frequency to second scan lines positioned in the second display area among the plurality of scan lines, wherein a hold frame of the multi-frequency mode includes a first section during which the first display area is driven, and a second section during which the second display area is driven, and wherein the driving controller has a control signal generator that outputs the clock signal in a normal power mode during the first section and outputs the clock signal in a low-power mode during the second section. ### Claim 18 (depends on 17) The electronic device of claim 17, wherein, during the first section, a frequency of the clock signal is a first clock frequency, and wherein, during the second section, the frequency of the clock signal is a second clock frequency lower than the first clock frequency. ### Claim 19 (depends on 17) The electronic device of claim 17, wherein, during the first section, the clock signal has a first pulse width, and wherein, during the second section, the clock signal has a second pulse width greater than the first pulse width. ### Claim 20 (depends on 17) The electronic device of claim 17, further comprising: a voltage generator, which generates a first voltage and a second voltage in response to a voltage control signal, wherein the driving controller outputs the voltage control signal corresponding to the operating mode and outputs the clock signal that swings between the first voltage and the second voltage, wherein, while the operating mode is a single-frequency mode, the first voltage has a first voltage level, and the second voltage has a second voltage level lower than the first voltage level, and wherein, while the operating mode is the multi-frequency mode, during the second section, the first voltage has a third voltage level lower than the first voltage level, and the second voltage has a fourth voltage level higher than the second voltage level.