# US 12,217,659 B2 · Display panel, driving method thereof and display device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,217,659 B2 - Document ID: US12217659B2 - Status: Granted - Kind: B2 - Application number: 18/108,284 - Filed: 2023-02-10 - Published: 2023-06-15 - Granted: 2025-02-04 - Earliest claimed: 2020-10-15 - Assignees: Xiamen Tianma Micro-Electronics Co., Ltd. - Applicants: Xiamen Tianma Micro-Electronics Co., Ltd. - Inventors: Qingjun Lai; Yihua Zhu; Ping An - Web page: https://patentgrep.com/patent/US12217659B2 ## CPC - G09G 3/32: semiconductive, e.g. using light-emitting diodes [LED] - G09G 3/3233: with pixel circuitry controlling the current through the light-emitting element - G09G 2300/043: Compensation electrodes or other additional electrodes in matrix displays related to distortions or compensation signals, e.g. for modifying TFT threshold voltage in column driver - G09G 2300/0819: used for counteracting undesired variations, e.g. feedback or autozeroing - G09G 2300/0842: forming a memory circuit, e.g. a dynamic memory with one capacitor - G09G 2300/0861: with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes - G09G 2310/0262: The addressing of the pixel, in a display other than an active matrix LCD, involving the control of two or more scan electrodes or two or more data electrodes, e.g. pixel voltage dependent on signals of two data electrodes - G09G 2310/08: Details of timing specific for flat panels, other than clock recovery - G09G 2320/0233: Improving the luminance or brightness uniformity across the screen - G09G 2320/045: Compensation of drifts in the characteristics of light emitting or modulating elements - G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00) ## Abstract Provided are a display panel, a driving method thereof and a display device. The display panel includes: a pixel circuit and a light-emitting element, where the pixel circuit includes a light emitting control module, a drive module and a compensation module; the light emitting control module includes a first light emitting control module configured to selectively provide a first power supply signal for the drive module; the drive module is configured to provide a drive current for the light-emitting element and comprises a drive transistor; the compensation module is configured to compensate a threshold voltage of the drive transistor; and a working process of the pixel circuit includes a light emitting stage and a bias stage. ## Claims ### Claim 1 A display panel, comprising: a pixel circuit and a light-emitting element, wherein the pixel circuit comprises a light emitting control module and a drive module; the drive module comprises a drive transistor; the light emitting control module comprises a first light emitting control module and a second light emitting control module, the first light emitting control module is connected between a first power supply signal terminal and an input terminal of the drive module, and the second light emitting control module is connected between an output terminal of the drive module and the light-emitting element; wherein a control terminal of the first light emitting control module is connected to a first light emitting control signal line to receive a first light emitting control signal; wherein a control terminal of the second light emitting control module is connected to a second light emitting control signal line to receive a second light emitting control signal; wherein a width of the first light emitting control signal line is larger than a width of the second light emitting control signal line; and wherein a working process of the pixel circuit comprises a light emitting stage and a bias stage, wherein in the light emitting stage, the first light emitting control module is on, and the second light emitting control module is on; and in the bias stage, the first light emitting control module is on, and the second light emitting control module is off. ### Claim 2 (depends on 1) The display panel of claim 1, wherein in the light emitting stage, a first power supply signal received by the first light emitting control module is PVDD1; in the bias stage, a first power supply signal received by the first light emitting control module is PVDD2; and PVDD2>PVDD1, or PVDD20; the pixel circuit further comprises a data write module, an input terminal of the data write module is configured to receive a data signal, and an output terminal of the data write module is connected to an input terminal of the drive module; the data write frame comprises a data write stage in which the data write module writes a data signal into a gate of the drive transistor; and the retention frame comprises no data write stage. ### Claim 4 (depends on 3) The display panel of claim 3, wherein at least one data write frame and/or at least one retention frame each comprises the bias stage, wherein a duration of the bias stage in the at least one retention frame is longer than a duration of the bias stage in the at least one data write frame. ### Claim 5 (depends on 3) The display panel of claim 3, wherein the display panel comprises at least two data write frames, and bias stages in the at least two data write frames have different durations. ### Claim 6 (depends on 5) The display panel of claim 5, wherein the display panel comprises first data write frames and second data write frames, n second data write frames are comprised between two adjacent ones of the first data write frames, wherein n≥1; and in the first data write frames, the bias stage has a duration of t7, and in the second data write frame, the bias stage has a duration of t8, wherein t7>t8≥0. ### Claim 7 (depends on 3) The display panel of claim 3, wherein the bias stage comprises m bias sub-stages in sequence, wherein m≥1; and in the m bias sub-stages, an interval between two adjacent bias sub-stages is a third interval stage in which the first light emitting control module is off. ### Claim 8 (depends on 7) The display panel of claim 7, wherein the bias stage comprises at least two third interval stages, and the at least two third interval stages have different durations. ### Claim 9 (depends on 7) The display panel of claim 7, wherein at least two of the m bias sub-stages have different durations. ### Claim 10 (depends on 1) The display panel of claim 1, wherein within one frame of the display panel, the working process of the pixel circuit comprises a pre-stage and the light emitting stage, wherein within at least one frame, the pre-stage of the pixel circuit comprises the bias stage. ### Claim 11 (depends on 10) The display panel of claim 10, wherein the pre-stage comprises a reset stage and the bias stage, and in the reset stage, a gate of the drive transistor receives a reset signal and a reset is performed; and/or the pre-stage comprises the bias stage and a data write stage, in the data write stage, a gate of the drive transistor receives a data signal, and the pixel circuit comprises a data write module configured to provide the data signal. ### Claim 12 (depends on 11) The display panel of claim 11, wherein the bias stage has a duration of t1, and the reset stage has a duration of t3, where t1>t3; or the bias stage has a duration of t1, and the data write stage has a duration of t5, wherein t1>t5. ### Claim 13 (depends on 11) The display panel of claim 11, wherein the pre-stage comprises the reset stage and the bias stage, and in the reset stage, the gate of the drive transistor receives the reset signal and the reset is performed; and wherein at an end of the reset stage, the gate of the drive transistor is disconnected from the reset signal, meanwhile, the first light emitting control module is turned on and the pixel circuit enters the bias stage; or between an end of the reset stage and a start of the bias stage, the pre-stage further comprises a first interval stage in which the gate of the drive transistor is disconnected from the reset signal and the first light emitting control module is off. ### Claim 14 (depends on 13) The display panel of claim 13, wherein the bias stage has a duration of t1, the reset stage has a duration of t3 and the first interval stage has a duration of t4, wherein t1>t4, or t3>t4. ### Claim 15 (depends on 11) The display panel of claim 11, wherein the pre-stage comprises the reset stage and the data write stage, and in the data write stage, the gate of the drive transistor receives the data signal, the pixel circuit comprises the data write module configured to provide the data signal; and wherein in the end of the bias stage, the first light emitting control module is turned off, meanwhile, the data write module is turned on, and the pixel circuit enters the data write stage; or from an end of the bias stage to a start of the data write stage, the pixel circuit comprises a second interval stage in which the first light emitting control module is off and the data write module is off. ### Claim 16 (depends on 15) The display panel of claim 15, wherein the bias stage has a duration of t1, the data write stage has a duration of t5, and the second interval stage has a duration of t6, wherein t1>t6, or t5>t6. ### Claim 17 (depends on 11) The display panel of claim 11, wherein the pre-stage comprises the reset stage and the bias stage, in the reset stage, the gate of the drive transistor receives the reset signal and the reset is performed; the reset stage comprises a first reset stage and a second reset stage; in the first reset stage whose time period does not overlap the time period of the bias stage, the gate of the drive transistor receives a first reset signal; and in at least part of the time period of the bias stage, the gate of the drive transistor receives a second reset signal, and the time period of the bias stage at least partially overlaps a time period of the second reset stage, wherein the first reset signal and the second reset signal have a same potential; or the first reset signal and the second reset signal have different potentials. ### Claim 18 (depends on 17) The display panel of claim 17, wherein an absolute value of a potential of the first reset signal is less than an absolute value of a potential of the second reset signal; wherein the drive transistor is a PMOS transistor, and the potential of the second reset signal is lower than the potential of the first reset signal; or the drive transistor is an NMOS transistor, and the potential of the second reset signal is higher than the potential of the first reset signal; or an absolute value of a potential of the first reset signal is great than an absolute value of a potential of the second reset signal; wherein the drive transistor is a PMOS transistor, and the potential of the second reset signal is lower than the potential of the first reset signal; or the drive transistor is an NMOS transistor, and the potential of the second reset signal is higher than the potential of the first reset signal. ### Claim 19 A display device, comprising a display panel, wherein the display panel comprises: a pixel circuit and a light-emitting element, wherein the pixel circuit comprises a light emitting control module and a drive module; the drive module comprises a drive transistor; the light emitting control module comprises a first light emitting control module and a second light emitting control module, the first light emitting control module is connected between a first power supply signal terminal and an input terminal of the drive module, and the second light emitting control module is connected between an output terminal of the drive module and the light-emitting element; wherein a control terminal of the first light emitting control module is connected to a first light emitting control signal line to receive a first light emitting control signal; wherein a control terminal of the second light emitting control module is connected to a second light emitting control signal line to receive a second light emitting control signal; wherein a width of the first light emitting control signal line is larger than a width of the second light emitting control signal line; and wherein a working process of the pixel circuit comprises a light emitting stage and a bias stage, wherein in the light emitting stage, the first light emitting control module is on, and the second light emitting control module is on; and in the bias stage, the first light emitting control module is on, and the second light emitting control module is off. ### Claim 20 (depends on 19) The display device of claim 19, wherein in the light emitting stage, a first power supply signal received by the first light emitting control module is PVDD1; in the bias stage, a first power supply signal received by the first light emitting control module is PVDD2; and PVDD2>PVDD1, or PVDD2