# US 12,217,328 B2 · Multistage collector for outputs in multiprocessor systems > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,217,328 B2 - Document ID: US12217328B2 - Status: Granted - Kind: B2 - Application number: 18/219,873 - Filed: 2023-07-10 - Published: 2023-11-02 - Granted: 2025-02-04 - Earliest claimed: 2011-09-16 - Assignees: Imagination Technologies Limited - Applicants: Imagination Technologies Limited - Inventors: James Alexander McCombe; Steven John Clohset; Jason Rupert Redgrave; Luke Tilman Peterson - Web page: https://patentgrep.com/patent/US12217328B2 ## CPC - G06T 1/60: Memory management - G06T 1/20: Processor architectures; Processor configuration, e.g. pipelining - G06T 15/06: Ray-tracing - G06T 2210/52: Parallel processing - G06T: IMAGE DATA PROCESSING OR GENERATION, IN GENERAL ## Abstract Aspects include a multistage collector to receive outputs from plural processing elements. Processing elements may comprise (each or collectively) a plurality of clusters, with one or more ALUs that may perform SIMD operations on a data vector and produce outputs according to the instruction stream being used to configure the ALU(s). The multistage collector includes substituent components each with at least one input queue, a memory, a packing unit, and an output queue; these components can be sized to process groups of input elements of a given size, and can have multiple input queues and a single output queue. Some components couple to receive outputs from the ALUs and others receive outputs from other components. Ultimately, the multistage collector can output groupings of input elements. Each grouping of elements (e.g., at input queues, or stored in the memories of component) can be formed based on matching of index elements. ## Claims ### Claim 1 A system comprising: a plurality of collector units for use in parallelized computing, each collector unit comprising: at least one input port configured to receive, from one or more computation units, data comprised of data elements associated with an index element; a memory configured to store one or more collections of data elements; at least one output port configured to output collections of data elements; and a packer configured to interface with the memory and being coupled to the at least one output port; wherein the packer is further configured to: identify an index element associated with each data element; and group the received data elements associated with the index elements into collections based on the index elements to form one or more further collection of data elements; wherein the plurality of collector units are arranged in an interconnected series. ### Claim 2 (depends on 1) The system according to claim 1, wherein the collector unit is configured to form collections of data elements, the collections being of a specific size. ### Claim 3 (depends on 1) The system according to claim 1, wherein the packer comprises: one or more arithmetic logic unit configured to perform single instruction multiple data operations on the received data to form collections of data elements to be output according to an instruction stream used to configure the one or more arithmetic logic units. ### Claim 4 (depends on 3) The system according to claim 3, wherein each collector unit is configured to receive outputs from an arithmetic logic unit of a further collector unit. ### Claim 5 (depends on 1) The system according to claim 1, wherein each collector unit is further configured to evict collections of data from its memory, responsive to a collection eviction process. ### Claim 6 (depends on 5) The system according to claim 5, wherein each collector unit further comprises an upstream status receiver configured to determine policies of the collection eviction process. ### Claim 7 (depends on 1) The system according to claim 1, wherein each collector unit is a multistage collector. ### Claim 8 (depends on 1) The system according to claim 1, wherein forming one or more further collections of data elements comprises collecting the data elements that reference the same index element by extracting each of the data elements from its pairing with an index element and grouping the extracted data elements referencing the same index element into larger groupings, each grouping maintaining an association with its respective index element. ### Claim 9 (depends on 1) The system according to claim 1, wherein each collector unit is configured to terminate the forming of collections of data elements for a specific index element grouping based on a heuristic. ### Claim 10 (depends on 1) The system of claim 1, wherein the system is a multiprocessor system. ### Claim 11 (depends on 10) The system according to claim 10, wherein the packer of each of the plurality of collector units comprises: one or more arithmetic logic unit configured to perform single instruction multiple data operations on the received data to produce collections of data elements to be output according to an instruction stream used to configure the one or more arithmetic logic units. ### Claim 12 (depends on 10) The system according to claim 10, wherein the plurality of collector units are arranged hierarchically to include a regular ratio between the input and output queues. ### Claim 13 (depends on 10) The system according to claim 10, wherein the plurality of collector units are clocked from a single reference clock. ### Claim 14 (depends on 10) The system according to claim 10, wherein the plurality of collector units are clocked from respective reference clocks. ### Claim 15 (depends on 10) The system according to claim 10, wherein of the plurality of collector units, a first collector unit is clocked at a higher frequency than a second collector unit. ### Claim 16 (depends on 10) The system according to claim 10, wherein the interconnected series of collector units is arranged in an inverted hierarchy, beginning with a layer of collector units receiving smaller packets and terminating with one or more collectors outputting one or more larger packets, each containing constituent data elements of a plurality of the smaller packets. ### Claim 17 (depends on 16) The system according to claim 16, wherein the interconnected series of collector units is configured to apply backpressure between collector units in different layers of the inverted hierarchy to regulate progress of collections through the plurality of collectors. ### Claim 18 (depends on 10) The system according to claim 10, wherein each of the plurality of collector units is further configured to evict collections of data from its memory, responsive to a collection eviction process. ### Claim 19 (depends on 18) The system according to claim 18, wherein each of the plurality of collector units comprises an upstream status receiver configured to determine policies of the collection eviction process.