# US 12,217,327 B2 · Multi-tile graphics processing unit

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- Number: US 12,217,327 B2
- Document ID: US12217327B2
- Status: Granted
- Kind: B2
- Application number: 17/978,426
- Filed: 2022-11-01
- Published: 2023-02-16
- Granted: 2025-02-04
- Earliest claimed: 2020-11-18
- Assignees: Intel Corporation
- Applicants: Intel Corporation
- Inventors: Michal Mrozek; Bartosz Dunajski; Ben Ashbaugh; Brandon Fliflet
- Web page: https://patentgrep.com/patent/US12217327B2

## CPC

- G06T 1/60: Memory management
- G06F 3/0604: {Improving or facilitating administration, e.g. storage management}
- G06F 3/0655: {Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices}
- G06F 3/0673: {Single storage device}
- G06F 12/0871: Allocation or management of cache space
- G06F 12/0875: with dedicated cache, e.g. instruction or stack
- G06T 1/20: Processor architectures; Processor configuration, e.g. pipelining
- G06T: IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

An apparatus to facilitate processing in a multi-tile device is disclosed. In one embodiment, the apparatus includes a graphics processor comprising a first semiconductor die including a first high-bandwidth memory (HBM) device, a second semiconductor die including a second HBM device, and a third semiconductor die coupled with the first semiconductor die and the second semiconductor die in a 2.5-dimensional (2.5D) arrangement. The third semiconductor die includes a graphics processing resource and a cache coupled with the graphics processing resource. The cache is configurable to cache data associated with memory accessed by the graphics processing resource and the graphics processing resource includes a general-purpose graphics processor core and a tensor core.

## Claims

### Claim 1

A graphics processor comprising:
a package assembly comprising a plurality of distinct chiplets and a plurality of interconnect structures, the plurality of distinct chiplets including:
a first chiplet comprising:
a first semiconductor die including a first high-bandwidth memory (HBM) device; and
a second semiconductor die including a second HBM device; and
a second chiplet comprising:
a third semiconductor die coupled with the first semiconductor die and the second semiconductor die in a 2.5-dimensional (2.5D) arrangement, the third semiconductor die including a graphics processing resource and a cache coupled with the graphics processing resource, wherein,
the cache is configured to cache data associated with memory accessed by the graphics processing resource, and
the graphics processing resource includes a general-purpose graphics processor core and a tensor core.

### Claim 2 (depends on 1)

The graphics processor of claim 1, the first semiconductor die including a first stack of HBM devices.

### Claim 3 (depends on 1)

The graphics processor of claim 1, the second semiconductor die including a second stack of HBM devices.

### Claim 4 (depends on 1)

The graphics processor of claim 1, wherein the cache is a level-2 (L2) cache memory.

### Claim 5 (depends on 4)

The graphics processor of claim 4, wherein the cache is a distributed cache having nodes interconnected via an interconnect network.

### Claim 6 (depends on 5)

The graphics processor of claim 5, wherein the cache is configured to cache data associated with a first memory access to the first HBM device and a second memory access to the second HBM device.

### Claim 7 (depends on 1)

The graphics processor of claim 1, wherein the general-purpose graphics processor core and tensor core support a single instruction multiple thread (SIMT) architecture.

### Claim 8 (depends on 7)

The graphics processor of claim 7, the general-purpose graphics processor core additionally including a ray-tracing core.

### Claim 9 (depends on 8)

The graphics processor of claim 8, wherein the general-purpose graphics processor core, tensor core, or ray-tracing core additionally support a single instruction multiple data (SIMD) architecture.

### Claim 10 (depends on 1)

The graphics processor of claim 1, further comprising a fourth semiconductor die coupled with the first semiconductor die, second semiconductor die, and third semiconductor die, the fourth semiconductor die including a level-3 (L3) cache.

### Claim 11

A system comprising:
an interconnect to a system interface; and
a multi-die graphics processor coupled with the interconnect, the multi-die graphics processor comprising:
a package assembly comprising a plurality of distinct chiplets and a plurality of interconnect structures, the plurality of distinct chiplets including:
a first chiplet comprising:
a first semiconductor die including a first high-bandwidth memory (HBM) device;
a second semiconductor die including a second HBM device; and
a second chiplet comprising:
a third semiconductor die coupled with the first semiconductor die and the second semiconductor die in a 2.5-dimensional (2.5D) arrangement, the third semiconductor die including a graphics processing resource and a cache coupled with the graphics processing resource,
wherein,
the cache is configured to cache data associated with memory accessed by the graphics processing resource, and
the graphics processing resource includes a general-purpose graphics processor core and a tensor core.

### Claim 12 (depends on 11)

The system of claim 11, the first semiconductor die including a first stack of HBM devices.

### Claim 13 (depends on 11)

The system of claim 11, the second semiconductor die including a second stack of HBM devices.

### Claim 14 (depends on 11)

The system of claim 11, wherein the cache is a level-2 (L2) cache memory.

### Claim 15 (depends on 14)

The system of claim 14, wherein the cache is a distributed cache having nodes interconnected via an interconnect network.

### Claim 16 (depends on 15)

The system of claim 15, wherein the cache is configured to cache data associated with a first memory access to the first HBM device and a second memory access to the second HBM device.

### Claim 17 (depends on 11)

The system of claim 11, wherein the general-purpose graphics processor core and tensor core support a single instruction multiple thread (SIMT) architecture.

### Claim 18 (depends on 17)

The system of claim 17, the general-purpose graphics processor core additionally including a ray-tracing core.

### Claim 19 (depends on 18)

The system of claim 18, wherein the general-purpose graphics processor core, tensor core, or ray-tracing core additionally support a single instruction multiple data (SIMD) architecture.

### Claim 20 (depends on 11)

The system of claim 11, further comprising a fourth semiconductor die coupled with the first semiconductor die, second semiconductor die, and third semiconductor die, the fourth semiconductor die including a level-3 (L3) cache.