# US 12,217,167 B2 · High performance computing system for deep learning > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,217,167 B2 - Document ID: US12217167B2 - Status: Granted - Kind: B2 - Application number: 16/595,992 - Filed: 2019-10-08 - Published: 2020-04-16 - Granted: 2025-02-04 - Earliest claimed: 2018-10-10 - Assignees: Samsung Electronics Co., Ltd. - Applicants: Samsung Electronics Co., Ltd. - Inventors: Minsoo Rhu; Youngeun Kwon - Web page: https://patentgrep.com/patent/US12217167B2 ## CPC - G06N 3/08: Learning methods - G06F 13/28: using burst mode transfer, e.g. direct memory access {DMA}, cycle steal (G06F13/32 takes precedence) - G06F 15/167: using a common memory, e.g. mailbox - G06F 15/17337: {Direct connection machines, e.g. completely connected computers, point to point communication networks (coupling between buses G06F13/4004)} - G06F 15/17375: {One dimensional, e.g. linear array, ring} - G06N 3/045: Combinations of networks - G06N 3/0464: Convolutional networks [CNN, ConvNet] - G06N 3/063: using electronic means - G06N 3/084: Backpropagation, e.g. using gradient descent - G06N 3/09: Supervised learning - G06N 3/098: Distributed learning, e.g. federated learning - G06N 3/10: Interfaces, programming languages or software development kits, e.g. for simulating neural networks - G06N: COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract A computing system includes a host processor, a plurality of accelerators that communicate with the host processor based on a communication interface, and a plurality of memory nodes that are connected with the plurality of accelerators through an interconnection network. A first data link is established between a first accelerator of the plurality of accelerators and a first memory node of the plurality of memory nodes, and a second data link is established between the first accelerator and a second memory node of the plurality of memory nodes. ## Claims ### Claim 1 A system comprising: a host processor; a plurality of accelerators configured to communicate with the host processor based on a communication interface; and a plurality of memory nodes distinguished from a host memory and is connected with the plurality of accelerators through an interconnection network, wherein the interconnection network is between the plurality of accelerators and the plurality of memory nodes and comprises data links through which the accelerators directly access the memory nodes without interaction with the host processor and the host memory, wherein a first accelerator of the plurality of accelerators directly accesses first and second memory nodes of the plurality of memory nodes through respective first and second of the data links of the plurality of data links of the interconnection network, wherein a second accelerator of the plurality of accelerators, connecting to the first memory node through a third data link, the second accelerator being different than the first accelerator, and wherein the first accelerator and the second accelerator directly exchange data with each other through the first memory node in which the first accelerator transfers data to the second accelerator through the first memory node, and the second accelerator transfers data to the first accelerator through the first memory node. ### Claim 2 (depends on 1) The system of claim 1, wherein a third of the data links is established between a second accelerator of the plurality of accelerators and the first memory node, and a fourth of the data links is established between the second accelerator and a third memory node of the plurality of memory nodes. ### Claim 3 (depends on 1) The system of claim 1, wherein the first memory node includes: a first memory module configured to store data transferred from the first accelerator through the first data link or to transfer stored data to the first accelerator through the first data link; and a second memory module configured to store data transferred from a second accelerator through the third data link or to transfer stored data to the second accelerator through the third data link. ### Claim 4 (depends on 3) The system of claim 3, wherein the first memory module includes a first direct memory access (DMA) engine allowing the first accelerator to directly access the first memory module, and wherein the second memory module includes a second DMA engine allowing the second accelerator to directly access the second memory module. ### Claim 5 (depends on 3) The system of claim 3, wherein the first memory node further includes a protocol engine configured to transfer data stored in the first memory module and the second memory module in compliance with a particular protocol. ### Claim 6 (depends on 1) The system of claim 1, wherein the interconnection network includes a ring network, and wherein each of the plurality of accelerators is configured to directly access at least two respective memory nodes. ### Claim 7 (depends on 1) The system of claim 1, wherein the first accelerator performs deep learning by using the first memory node and the second memory node. ### Claim 8 (depends on 1) The system of claim 1, wherein the first memory node includes: a first direct memory access (DMA) engine allowing the first accelerator to directly access the first memory node; a second DMA engine allowing the second accelerator to directly access the first memory node; a first memory controller configured to control the first DMA; and a second memory controller configured to control the second DMA. ### Claim 9 (depends on 1) The system of claim 1, wherein each accelerator is directly connected to a previous memory node and a next memory node in a ring arrangement, and each memory node is directly connected to a previous accelerator and a next accelerator in the ring arrangement and formed a closed loop. ### Claim 10 A system comprising: a host processor configured to generate a learning command for a plurality of input data; a first accelerator configured to perform an operation on first input data of the plurality of input data based on neural network variables in response to the learning command and to generate a first operation result and a second operation result; a second accelerator configured to perform an operation on second input data of the plurality of input data based on neural network variables in response to the learning command and to generate a third operation result and a fourth operation result; a first memory node of a plurality of memory nodes configured to store the first operation result transferred directly from the first accelerator through a first data link, the plurality of memory nodes is distinguished from a host memory; a second memory node configured to store the second operation result transferred directly from the first accelerator through a second data link; and a third memory node configured to store the fourth operation result transferred from the second accelerator through a third data link, wherein the first accelerator, without interaction with the host processor and the host memory, directly accesses the first memory node through the first data link and directly accesses the second memory node through the second data link, and wherein the first memory node stores the third operation result transferred from the second accelerator through a fourth data link. ### Claim 11 (depends on 10) The system of claim 10, wherein the first memory node includes: a first memory module configured to store the first operation result through the first data link; and a second memory module configured to store the third operation result through the fourth data link. ### Claim 12 (depends on 11) The system of claim 11, wherein the first memory module includes a first direct memory access (DMA) engine allowing the first accelerator to directly access the first memory module, and wherein the second memory module includes a second DMA engine allowing the second accelerator to directly access the second memory module. ### Claim 13 (depends on 11) The system of claim 11, wherein the first memory node further includes a protocol engine configured to transfer the first operation result stored in the first memory module to the first accelerator and the third operation result stored in the second memory module to the second accelerator in compliance with a particular protocol. ### Claim 14 (depends on 10) The system of claim 10, wherein the first accelerator updates the neural network variables by using the first operation result stored in the first memory node and the second operation result stored in the second memory node. ### Claim 15 (depends on 10) The system of claim 10, wherein the system includes a ring network, wherein each of the accelerators is configured to directly access at least two respective memory nodes, and wherein the first memory node includes: a first direct memory access (DMA) engine allowing the first accelerator to directly access the first memory node; a second DMA engine allowing a second accelerator to directly access the first memory node; a first memory controller configured to control the first DMA; and a second memory controller configured to control the second DMA. ### Claim 16 A system comprising: a host processor; a plurality of accelerators configured to communicate with the host processor based on a communication interface; and a plurality of memory nodes distinguished from a host memory and is connected with the plurality of accelerators through an interconnection network, wherein the interconnection network is between the plurality of accelerators and the plurality of memory nodes and comprises data links through which the accelerators directly access the memory nodes without interaction with the host processor and the host memory, wherein a first memory node of the plurality of memory nodes directly accesses a first accelerator through a first of the data links of the interconnection network and directly accesses a second accelerator of the plurality of accelerators through a second of data links of the interconnection network, wherein the second accelerator is different than the first accelerator, and wherein the first accelerator and the second accelerator directly exchange data with each other through the first memory node in which the first accelerator transfers data to the second accelerator through the first memory node, and the second accelerator transfers data to the first accelerator through the first memory node. ### Claim 17 (depends on 16) The system of claim 16, wherein the first memory node includes: a first memory module configured to store data transferred from the first accelerator through the first data link or to transfer stored data to the first accelerator through the first data link; and a second memory module configured to store data transferred from the second accelerator through the second data link or to transfer stored data to the second accelerator through the second data link. ### Claim 18 (depends on 17) The system of claim 17, wherein the first memory module includes a first direct memory access (DMA) engine allowing the first accelerator to directly access the first memory module, and wherein the second memory module includes a second DMA engine allowing the second accelerator to directly access the second memory module. ### Claim 19 (depends on 16) The system of claim 16, wherein the first memory node includes: a first direct memory access (DMA) engine allowing the first accelerator to directly access the first memory node; a second DMA engine allowing a second accelerator to directly access the first memory node, a first memory controller configured to control the first DMA; and a second memory controller configured to control the second DMA.