# US 12,217,165 B2 · Concurrent write and verify operations in an analog neural memory

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- Number: US 12,217,165 B2
- Document ID: US12217165B2
- Status: Granted
- Kind: B2
- Application number: 17/190,376
- Filed: 2021-03-02
- Published: 2022-03-03
- Granted: 2025-02-04
- Earliest claimed: 2020-08-25
- Assignees: Silicon Storage Technology, Inc.
- Applicants: Silicon Storage Technology, Inc.
- Inventors: Hieu Van Tran
- Web page: https://patentgrep.com/patent/US12217165B2

## CPC

- G06N 3/065: Analogue means
- G11C 16/3459: {Circuits or methods to verify correct programming of nonvolatile memory cells}
- G06N 3/045: Combinations of networks
- G06N 3/0464: Convolutional networks [CNN, ConvNet]
- G11C 11/40: using transistors
- G11C 11/54: using elements simulating biological cells, e.g. neuron
- G11C 16/10: Programming or data input circuits
- G11C 16/12: Programming voltage switching circuits
- G11C 16/24: Bit-line control circuits
- G11C 16/26: Sensing or reading circuits; Data output circuits
- G06N: COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

Numerous embodiments of analog neural memory systems that enable concurrent write and verify operations are disclosed. In some embodiments, concurrent operations occur among different banks of memory. In other embodiments, concurrent operations occur among different blocks of memory, where each block comprises two or more banks of memory. The embodiments substantially reduce the timing overhead for weight writing and verifying operations in analog neural memory systems.

## Claims

### Claim 1

An analog neural memory system comprising:
a first bank comprising a first array of non-volatile memory cells;
a second bank comprising a second array of non-volatile memory cells;
writing circuitry shared by the first bank and the second bank and selectively coupled to the first bank by a first write multiplexor and selectively coupled to the second bank by a second write multiplexor;
sensing circuitry shared by the first bank and the second bank and selectively coupled to the first bank by a first read multiplexor and selectively coupled to the second bank by a second read multiplexor;
a column multiplexor to connect, when enabled, bit lines in the first array to bit lines in the second array to enable control of the first array and the second array as a single array; and
control circuitry for concurrently performing a write operation using the writing circuitry on one of the first bank and the second bank and a verify operation using the sensing circuitry on the other of the first bank and the second bank.

### Claim 2 (depends on 1)

The system of claim 1, wherein the first bank comprises a third array of non-volatile memory cells and the second bank comprises a fourth array of non-volatile memory cells.

### Claim 3 (depends on 1)

The system of claim 1, wherein the non-volatile memory cells in the first bank and the non-volatile memory cells in the second bank are stacked gate non-volatile memory cells.

### Claim 4 (depends on 1)

The system of claim 1, wherein the non-volatile memory cells in the first bank and the non-volatile memory cells in the second bank are split-gate non-volatile memory cells.

### Claim 5

A method of performing concurrent write and verify operations in an analog neural memory comprising a first bank comprising a first array of non-volatile memory cells and a second bank comprising a second array of non-volatile memory cells, the method comprising:
concurrently performing a write operation on one of the first bank and the second bank and a verify operation on the other of the first bank and the second bank; and
enabling a column multiplexor to connect bit lines of the first array to bit lines of the second array;
controlling the first array and the second array as a single array.

### Claim 6 (depends on 5)

The method of claim 5, wherein the first bank comprises a third array of non-volatile memory cells and the second bank comprises a fourth array of non-volatile memory cells.

### Claim 7 (depends on 5)

The method of claim 5, wherein the non-volatile memory cells in the first bank and the non-volatile memory cells in the second bank are stacked gate non-volatile memory cells.

### Claim 8 (depends on 5)

The method of claim 5, wherein the non-volatile memory cells in the first bank and the non-volatile memory cells in the second bank are split-gate non-volatile memory cells.