# US 12,217,164 B2 · Neural network and its information processing method, information processing system

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- Number: US 12,217,164 B2
- Document ID: US12217164B2
- Status: Granted
- Kind: B2
- Application number: 16/964,435
- Filed: 2018-02-24
- Published: 2021-02-18
- Granted: 2025-02-04
- Earliest claimed: 2018-01-24
- Assignees: Tsinghua University
- Applicants: Tsinghua University
- Inventors: Xinyi Li; Huaqiang Wu; He Qian; Bin Gao; Sen Song; Qingtian Zhang
- Web page: https://patentgrep.com/patent/US12217164B2

## CPC

- G06N 3/065: Analogue means
- G06N 3/049: Temporal neural networks, e.g. delay elements, oscillating neurons or pulsed inputs
- G06N 3/084: Backpropagation, e.g. using gradient descent
- G06N: COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS

## Abstract

A neural network and its information processing method, information processing system. The neural network includes N layers of neuron layers connected to each other one by one, except for a first layer of neuron layer, each of the neurons of the other neuron layers includes m dendritic units and one hippocampal unit; the dendritic unit includes a resistance value graded device, the hippocampal unit includes a resistance value mutation device, and the m dendritic units can be provided with different threshold voltage or current, respectively; and the neurons on the nth layer neuron layer are connected to the m dendritic units of the neurons on the n+1th layer neuron layer; wherein N is an integer larger than 3, m is an integer larger than 1, n is an integer larger than 1 and less than N.

## Claims

### Claim 1

A neural network circuit, comprising:
N neuron layers connected one by one, wherein except for a first neuron layer, each neuron in other neuron layers comprises m dendrite units and one soma unit;
wherein the dendrite units each comprises a capacitor and a diode in series and a resistance gradient element, the soma unit comprises a resistance mutation element and an oscillating circuit, and the m dendrite units are configured with different threshold voltages or currents respectively; and
neurons in an n-th neuron layer are respectively connected to the m dendrite units of each neuron in an (n+1)th neuron layer;
wherein N is an integer greater than or equal to 2, m is an integer greater than 1, n is an integer greater than or equal to 1 and less than N;
wherein outputs of the m dendrite units conform to the following function:
y
=
{
x
,
a
=
0
e
ax
-
1
e
a
-
1
,
a
>
0
where a denotes a nonlinear coefficient, which comprises a threshold voltage or current of the dendrite unit; x represents an input of the m dendrite units, and y represents the outputs of the m dendrite units.

### Claim 2 (depends on 1)

The neural network circuit according to claim 1, wherein the m dendrite units are connected in various series-parallel connection, and then connected in series with the soma unit.

### Claim 3 (depends on 1)

The neural network circuit according to claim 1, wherein an output oscillation frequency of the soma unit conforms to the following function:
y
=
{
2
*
sigmoid
⁡
(
x
-
c
)
-
1
,
x
>
c
0
,
x
≤
c
where c denotes a threshold voltage or current of the soma unit, the sigmoid function is defined as:
g
⁡
(
z
)
=
1
1
+
e
-
z
where
⁢
⁢
z
=
x
-
c
.
x1 represents an input of the soma unit, and y1 represents the output oscillation frequency of the soma unit.

### Claim 4 (depends on 1)

The neural network circuit according to claim 1, wherein the n-th neuron layer is connected to the (n+1)th neuron layer by a synapse unit.

### Claim 5 (depends on 4)

The neural network circuit according to claim 4, wherein the synapse unit comprises a memristor array.

### Claim 6 (depends on 1)

An information processing system, comprising: the neural network circuit according to claim 1, an input circuit, an output circuit, and at least one hardware processor;
wherein the input circuit is configured to process data signals into input signals required by the neural network circuit;
the output circuit is configured to process an output outputted by the neural network circuit and send a process result to the at least one hardware processor; and
the at least one hardware processor is configured to optimize parameters of a synapse unit of the neural network circuit and to apply voltage signals to the neural network circuit via signal lines.

### Claim 7 (depends on 1)

An information processing method for the neural network circuit according to claim 1, comprising:
dividing input signals of each neuron in the (n+1)th neuron layer into m groups, and sending the m groups of input signals to the m dendrite units of each neuron respectively;
performing a nonlinear filtering operation on the m groups of input signals through the m dendrite units; and
performing a data processing on the input signals after performing of the nonlinear filtering operation, and then sending the input signals after performing of the data processing to the soma unit for a further data processing.

### Claim 8 (depends on 7)

The information processing method according to claim 7, wherein the nonlinear filtering operation comprises:
setting threshold voltages or currents for the m dendrite units respectively;
in a case where the input signals are greater than the threshold voltages or currents, performing an operation to the input signals; and
in a case where the input signals are less than the threshold voltages or currents, performing no operation to the input signals.

### Claim 9 (depends on 7)

The information processing method according to claim 7, further comprising:
after the soma unit performs the data processing on outputs of the dendrite units, transmitting signals to an (n+2)th neuron layer through an axon unit.

### Claim 10 (depends on 7)

The information processing method according to claim 7, further comprising:
after the dendrite units perform the data processing, turning off the input signals to restore the dendrite units and the soma unit to respective initial states.

### Claim 11 (depends on 7)

The information processing method according to claim 7, further comprising:
computing input signals of each neuron in the (n+1)th neuron layer through a synapse unit.