# US 12,217,162 B2 · Integrated circuit chip apparatus > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,217,162 B2 - Document ID: US12217162B2 - Status: Granted - Kind: B2 - Application number: 18/085,273 - Filed: 2022-12-20 - Published: 2023-04-20 - Granted: 2025-02-04 - Earliest claimed: 2017-12-14 - Assignees: Cambricon Technologies Corporation Limited - Applicants: Cambricon Technologies Corporation Limited - Inventors: Shaoli Liu; Xinkai Song; Bingrui Wang; Yao Zhang; Shuai Hu - Web page: https://patentgrep.com/patent/US12217162B2 ## CPC - G06N 3/063: using electronic means - G06F 7/483: Computations with numbers represented by a non-linear combination of denominational numbers, e.g. rational numbers, logarithmic number system or floating-point numbers {(G06F7/4806, G06F7/4824, G06F7/49, G06F7/491, G06F7/544 take precedence)} - G06F 7/5443: {Sum of products (for applications thereof, see the relevant places, e.g. G06F17/10, H03H17/00)} - G06F 17/153: {Multidimensional correlation or convolution} - G06F 17/16: Matrix or vector computation {, e.g. matrix-matrix or matrix-vector multiplication, matrix factorization (matrix transposition G06F7/78)} - G06N 3/04: Architecture, e.g. interconnection topology - G06N 3/044: Recurrent networks, e.g. Hopfield networks - G06N 3/045: Combinations of networks - G06N 3/0464: Convolutional networks [CNN, ConvNet] - G06N 3/06: Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons - G06N 3/08: Learning methods - H10W 90/00: Package configurations - G06F 2207/4824: Neural networks - G06N: COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract Provided are an integrated circuit chip apparatus and a related product, the integrated circuit chip apparatus being used for executing a multiplication operation, a convolution operation or a training operation of a neural network. The present technical solution has the advantages of a small amount of calculation and low power consumption. ## Claims ### Claim 1 An integrated circuit chip apparatus comprising: a main processing circuit and a plurality of basic processing circuits, wherein the plurality of basic processing circuits are configured to perform a first set of neural network computations in parallel on data transferred by the main processing circuit to obtain a plurality of computation results, and transfer the plurality of computation results to the main processing circuit, and the main processing circuit is configured to perform a second set of neural network computations in series on the plurality of computation results. ### Claim 2 (depends on 1) The integrated circuit chip apparatus of claim 1, wherein the main processing circuit or at least one of the plurality of basic processing circuits includes a data type conversion circuit configured to convert data between a floating point data type and a fixed point data type. ### Claim 3 (depends on 2) The integrated circuit chip apparatus of claim 2, wherein the main processing circuit is further configured to: receive a data block; and convert the data block to a fixed point data block using the data type conversion circuit. ### Claim 4 (depends on 3) The integrated circuit chip apparatus of claim 3, wherein the main processing circuit is further configured to: divide the fixed point data block into a distribution data block and a broadcasting data block; partition the distribution data block to obtain a plurality of basic data blocks; distribute the plurality of basic data blocks to the plurality of basic processing circuits; and broadcast the broadcasting data block to the plurality of basic processing circuits. ### Claim 5 (depends on 4) The integrated circuit chip apparatus of claim 4, wherein the basic processing circuits are further configured to: perform the first set of neural network computations on the basic data blocks and the broadcasting data block in the fixed point data type to obtain the plurality of computation results. ### Claim 6 (depends on 5) The integrated circuit chip apparatus of claim 5, wherein the main processing circuit is further configured to: convert the plurality of computation results to the floating point data type; and perform the second set of neural network computations on the computation results in the floating point data type. ### Claim 7 (depends on 1) The integrated circuit chip apparatus of claim 1, wherein the main processing circuit is further configured to: receive a data block; divide the data block into a distribution data block and a broadcasting data block; partition the distribution data block to obtain a plurality of basic data blocks; distribute the plurality of basic data blocks to the plurality of basic processing circuits; and broadcast the broadcasting data block to the plurality of basic processing circuits. ### Claim 8 (depends on 7) The integrated circuit chip apparatus of claim 7, wherein the basic processing circuits are further configured to: convert the basic data blocks and the broadcasting data block into data blocks of a fixed point data type; and perform the first set of neural network computations on the basic data blocks and the broadcasting data block in the fixed point data type to obtain fixed point computation results. ### Claim 9 (depends on 8) The integrated circuit chip apparatus of claim 8, wherein the basic processing circuits are further configured to: convert the computation results from the fixed point data type to a floating point data type; and transfer the computation results in the floating point data type to the main processing circuit. ### Claim 10 (depends on 8) The integrated circuit chip apparatus of claim 8, wherein the basic processing circuits are further configured to: transfer the computation results in fixed point data type to the main processing circuit, wherein the main processing circuit is further configured to: convert the plurality of computation results to a floating point data type; and perform the second set of neural network computations on the computation results in the floating point data type. ### Claim 11 (depends on 7) The integrated circuit chip apparatus of claim 7, wherein the main processing circuit is configured to broadcast the broadcasting data block as a whole to the plurality of basic processing circuits. ### Claim 12 (depends on 7) The integrated circuit chip apparatus of claim 7, wherein the broadcasting data block is a multiplier data block and the distribution data block a multiplicand data block. ### Claim 13 (depends on 7) The integrated circuit chip apparatus of claim 7, wherein the broadcasting data block is an input data block for convolution and the distribution data block is a convolution kernel. ### Claim 14 (depends on 1) The integrated circuit chip apparatus of claim 1, wherein the main processing circuit includes a main register or a main on-chip caching circuit, and each of the plurality of basic processing circuits includes a basic register or a basic on-chip caching circuit. ### Claim 15 (depends on 1) The integrated circuit chip apparatus of claim 1, wherein the main processing circuit includes one or more of a vector computing unit circuit, an arithmetic and logic unit circuit, an accumulator circuit, a matrix transposition circuit, a direct memory access circuit, a data type conversion circuit, or a data rearrangement circuit. ### Claim 16 (depends on 1) The integrated circuit chip apparatus of claim 1, wherein the first set of neural network computations are inner product computations, wherein the second set of neural computations are accumulation computations that accumulate the computation results obtained by the inner product computations. ### Claim 17 (depends on 1) The integrated circuit chip apparatus of claim 1, further comprising: a branch processing circuit, wherein the branch processing circuit is located between the main processing circuit and at least one basic processing circuit, wherein the branch processing circuit is configured to forward data between the main processing circuit and at least one basic processing circuit. ### Claim 18 A processing system, comprising: a neural network computing apparatus; a general interconnection interface; and a general-purpose processing apparatus connected to the neural network computing apparatus via the general interconnection interface, wherein the neural network computing apparatus further comprises: a main processing circuit and a plurality of basic processing circuits, wherein the plurality of basic processing circuits are configured to perform a first set of neural network computations in parallel on data transferred by the main processing circuit to obtain a plurality of computation results, and transfer the plurality of computation results to the main processing circuit, and the main processing circuit is configured to perform a second set of neural network computations in series on the plurality of computation results. ### Claim 19 A method for performing neural network operations using an integrated circuit chip apparatus comprising a main processing circuit, and a plurality of basic processing circuits, the method comprising: performing, by the plurality of basic processing circuits, a first set of neural network computations in parallel on data transferred by the main processing circuit to obtain a plurality of computation results, and transfer the plurality of computation results to the main processing circuit, and performing, by the main processing circuit, a second set of neural network computations in series on the plurality of computation results. ### Claim 20 (depends on 19) The method of claim 19, wherein the main processing circuit or at least one of the plurality of basic processing circuits includes a data type conversion circuit, wherein the method further comprises: converting data, by the data type conversion circuit, between a floating point data type and a fixed point data type.