# US 12,217,151 B2 · Layout parasitics and device parameter prediction using graph neural networks

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- Number: US 12,217,151 B2
- Document ID: US12217151B2
- Status: Granted
- Kind: B2
- Application number: 18/295,145
- Filed: 2023-04-03
- Published: 2023-07-27
- Granted: 2025-02-04
- Earliest claimed: 2019-11-27
- Assignees: NVIDIA Corporation
- Applicants: NVIDIA Corp.
- Inventors: Haoxing Ren; George Ferenc Kokai; Ting Ku; Walker Joseph Turner
- Web page: https://patentgrep.com/patent/US12217151B2

## CPC

- G06F 30/398: Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] (optical proximity correction [OPC] design processes G03F1/36)
- G06N 3/045: Combinations of networks
- G06F 16/9024: {Graphs; Linked lists (G06F16/9027 takes precedence)}
- G06F 17/16: Matrix or vector computation {, e.g. matrix-matrix or matrix-vector multiplication, matrix factorization (matrix transposition G06F7/78)}
- G06F 30/27: using machine learning, e.g. artificial intelligence, neural networks, support vector machines [SVM] or training a model
- G06N 3/04: Architecture, e.g. interconnection topology
- G06N 3/0499: Feedforward networks
- G06N 3/082: modifying the architecture, e.g. adding, deleting or silencing nodes or connections
- G06N 3/09: Supervised learning
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- G06N: COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS

## Abstract

A graph neural network to predict net parasitics and device parameters by transforming circuit schematics into heterogeneous graphs and performing predictions on the graphs. The system may achieve an improved prediction rate and reduce simulation errors.

## Claims

### Claim 1

A system comprising:
at least one graph neural network;
graph generation logic configured to transform a circuit netlist into a graph; and embedding logic configured to generate a node embedding for the graph in the at least one graph neural network, the node embedding formed by concatenating previously generated node embeddings with aggregated neighbor embeddings, the node embedding configured with different edge types of the graph grouped independently for processing by different attention layers of the at least one graph neural network, wherein the at least one graph neural network is configured to transform edges of the graph into parasitic resistance predictions for the circuit netlist.

### Claim 2 (depends on 1)

The system of claim 1, further comprising:
a plurality of graph neural networks each configured to transform the node embeddings into a different range of parasitic prediction values for the circuit netlist.

### Claim 3 (depends on 2)

The system of claim 2, wherein each of the plurality of graph neural networks are configured to form a node embedding for a next network layer by applying weights of the next network layer to a unified vector generated by combining outputs of the attention layers.

### Claim 4 (depends on 2)

The system of claim 2, wherein the parasitic prediction values are capacitive parasitic predictions.

### Claim 5 (depends on 3)

The system of claim 3, wherein the ranges have a common base level.

### Claim 6 (depends on 1)

The system of claim 1, wherein the at least one graph neural network is configured to transform the graph into parasitic predictions and device parameter predictions for the circuit netlist.

### Claim 7 (depends on 6)

The system of claim 6, further comprising:
a circuit simulator configured to receive the parasitic predictions and the device parameter predictions from the at least one graph neural network.

### Claim 8 (depends on 1)

The system of claim 1, wherein the graph comprises:
device nodes and net nodes; and
a plurality of heterogeneous edge types between the device nodes and the net nodes.

### Claim 9 (depends on 8)

The system of claim 8, wherein the heterogeneous edge types comprise net to transistor drain edges, net to transistor gate edges, transistor drain to net edges, and transistor gate to net edges.

### Claim 10 (depends on 8)

The system of claim 8, wherein:
the graph excludes edges between the device nodes and power rails and between the device nodes and ground rails.

### Claim 11 (depends on 1)

The system of claim 1, wherein:
the embedding logic is configured to sum vectors for groups of multiple edges of the graph into individually weighted vectors;
the at least one graph neural network is configured to:
apply a self-attention layer separately to the individually weighted vectors for each group; and
combine outputs of the self-attention layers for groups representing a same edge type into an output vector.

### Claim 12

A circuit simulator comprising:
a graphics processing unit;
at least one graph neural network;
a non-transitory machine-readable media comprising instructions that, when applied to the graphics processing unit: generate a node embedding in a graph neural network for a graph representing a circuit, the node embedding formed by concatenating previously generated node embeddings with aggregated neighbor embeddings, the node embeddings configured with different edge types of the graph grouped independently for processing by different attention layers of the graph neural network; and operate the at least one graph neural network to transform edges of the graph into parasitic predictions for the circuit, wherein the instructions, when applied to the graphics processing unit, operate the at least one graph neural network to transform edges of the graph into parasitic resistance predictions for the circuit.

### Claim 13 (depends on 12)

The circuit simulator of claim 12, wherein the instructions, when applied to the graphics processing unit, operate a plurality of graph neural networks to transform the node embeddings into a plurality of different ranges of parasitic prediction values for the circuit.

### Claim 14 (depends on 13)

The circuit simulator of claim 13, wherein the parasitic prediction values are capacitive parasitic predictions.

### Claim 15 (depends on 13)

The circuit simulator of claim 13, wherein the ranges have a common base level.

### Claim 16 (depends on 12)

The circuit simulator of claim 12, wherein the instructions, when applied to the graphics processing unit, operate the at last one graph neural network to transform the graph into parasitic predictions and device parameter predictions for the circuit.

### Claim 17 (depends on 12)

The circuit simulator of claim 12, wherein the graph comprises:
transistor device nodes and net nodes; and
a plurality of heterogeneous edge types between the transistor device nodes and the net nodes.

### Claim 18 (depends on 17)

The circuit simulator of claim 17, wherein the heterogeneous edge types comprise net to transistor drain edges, net to transistor gate edges, transistor drain to net edges, and transistor gate to net edges.