# US 12,217,129 B2 · Integrating circuit elements in a stacked quantum computing device

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- Number: US 12,217,129 B2
- Document ID: US12217129B2
- Status: Granted
- Kind: B2
- Application number: 17/902,695
- Filed: 2022-09-02
- Published: 2023-01-05
- Granted: 2025-02-04
- Earliest claimed: 2017-03-13
- Assignees: Google Inc.
- Applicants: Google LLC
- Inventors: Julian Shaw Kelly; Joshua Yousouf Mutus
- Web page: https://patentgrep.com/patent/US12217129B2

## CPC

- G06N 10/40: Physical realisations or architectures of quantum processors or components for manipulating qubits, e.g. qubit coupling or qubit control
- G06N 10/00: Quantum computing, i.e. information processing based on quantum-mechanical phenomena
- H10N 60/20: Permanent superconducting devices
- H10N 69/00: Integrated devices, or assemblies of multiple devices, comprising at least one superconducting element covered by group H10N60/00
- H10W 20/423: {Shielding layers}
- H10W 90/00: Package configurations
- H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/255: {of outermost layers of multilayered bumps, e.g. material of a coating}
- H10W 90/722: {between stacked chips}
- G06N: COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
- H10N: ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A stacked quantum computing device including a first chip that includes a first dielectric substrate and a superconducting qubit on the first dielectric substrate, and a second chip that is bonded to the first chip and includes a second dielectric substrate, a qubit readout element on the second dielectric substrate, a control wire on the second dielectric substrate, a dielectric layer covering the control wire, and a shielding layer covering the dielectric layer.

## Claims

### Claim 1

A method of bonding a first chip to a second chip, the method comprising:
providing the first chip, wherein the first chip comprises a first dielectric substrate and a qubit device on the first dielectric substrate, wherein the qubit device comprises a first superconductor layer;
providing the second chip, wherein the second chip comprises a second dielectric substrate, a qubit readout element on the second dielectric substrate, a control wire on the second dielectric substrate and separate from the qubit readout element, a dielectric layer covering the control wire, and a shielding layer covering the dielectric layer;
aligning the first chip to the second chip such that
a portion of the control wire overlaps a first portion of the first superconductor layer the qubit,
the qubit readout element overlaps a second portion of the first superconductor layer of the qubit device,
and the shielding layer is arranged between the portion of the control wire and the portion of the first superconductor layer of the qubit device to reduce crosstalk between the control wire and the qubit device; and
bonding the first chip to the second chip.

### Claim 2 (depends on 1)

The method of claim 1, wherein the second chip comprises a plurality of dielectric layers and a plurality of superconductor layers arranged in a stack overlying the control wire, wherein the stack is between the control wire and the shielding layer.

### Claim 3 (depends on 2)

The method of claim 2, wherein the plurality of superconductor layers in the stack define wiring elements.

### Claim 4 (depends on 2)

The method of claim 2, wherein the stack comprises a microstrip, a multi-layer stripline, or a combination thereof.

### Claim 5 (depends on 2)

The method of claim 2, wherein at least two superconductor layers of the plurality of superconductor layers are coupled to one another through a via interconnect.

### Claim 6 (depends on 2)

The method of claim 2, wherein an uppermost superconductor layer of the plurality of superconductor layers comprises the control wire and the shielding layer, and the control wire comprises a qubit control element.

### Claim 7 (depends on 6)

The method of claim 6, wherein the uppermost superconductor layer covers a sidewall of the stack.

### Claim 8 (depends on 6)

The method of claim 6, comprising aligning the first chip to the second chip such that the qubit control element overlaps the qubit device on the first dielectric substrate.

### Claim 9 (depends on 1)

The method of claim 1, wherein superconductor bump bonds couple a ground plane on the first chip to a ground plane on the second chip.

### Claim 10 (depends on 1)

The method of claim 1, comprising bonding the first chip to the second chip with superconductor bump bonds.

### Claim 11 (depends on 1)

The method of claim 1, wherein the qubit readout element comprises a first part that overlaps the second portion of the first superconductor layer of the qubit device.

### Claim 12 (depends on 11)

The method of claim 11, wherein the dielectric layer of the second chip comprises an opening through which a surface of the first part of the qubit readout element is exposed and faces the qubit device.

### Claim 13 (depends on 12)

The method of claim 12, wherein the qubit readout element comprises a second part that is coupled to the first part.

### Claim 14 (depends on 13)

The method of claim 13, wherein the first part of the qubit readout element comprises a pad element, and the second part comprises a resonator.

### Claim 15 (depends on 14)

The method of claim 14, wherein the dielectric layer of the second chip covers the resonator.

### Claim 16 (depends on 15)

The method of claim 15, wherein the resonator does not overlap the qubit device.