Distributed mechanism for fine-grained test power control

An integrated circuit, comprising:

• a set of processor cores, wherein each processor core of the set of processor cores comprises:
• built-in self-test (BIST) logic circuitry;
• and
• multiple memory blocks coupled to the BIST logic circuitry;
• multiple power control circuitry, wherein each power control circuitry of the multiple power control circuitry is coupled to a respective processor core of the set of processor cores;
• multiple isolation circuitry, wherein each isolation circuitry of the multiple isolation circuitry is coupled to a respective processor core of the set of processor cores;
• and
• a built-in-self repair (BISR) controller coupled to each processor core of the set of processor cores, to each power control circuitry of the multiple power control circuitry, and to each isolation circuitry of the multiple isolation circuitry, wherein the BISR controller is configured to:
• receive multiple test power control scenarios that are associated with BIST memory testing of the set of processor cores, wherein the multiple test power control scenarios comprise a hierarchical order of applying one or more test power control scenarios to the set of processor cores;
• dynamically apply, according to the hierarchical order, the one or more test power control scenarios on the set of processor cores;
• perform BIST memory testing of at least one memory block of the multiple memory blocks associated with each processor core of the set of processor cores;
• and
• receive a result of the BIST memory testing.