# US 12,217,101 B2 · Methods and apparatus to configure heterogenous components in an accelerator > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,217,101 B2 - Document ID: US12217101B2 - Status: Granted - Kind: B2 - Application number: 18/309,650 - Filed: 2023-04-28 - Published: 2023-10-19 - Granted: 2025-02-04 - Earliest claimed: 2019-08-15 - Assignees: Intel Corporation - Applicants: Intel Corporation - Inventors: Michael Behar; Moshe Maor; Ronen Gabbai; Roni Rosner; Zigi Walter; Oren Agam - Web page: https://patentgrep.com/patent/US12217101B2 ## CPC - G06F 9/5083: {Techniques for rebalancing the load in a distributed system} - G06F 8/433: {Dependency analysis; Data or control flow analysis} - G06F 9/5027: {the resource being a machine, e.g. CPUs, Servers, Terminals} - G06F 16/9024: {Graphs; Linked lists (G06F16/9027 takes precedence)} - G06N 3/044: Recurrent networks, e.g. Hopfield networks - G06N 3/0442: characterised by memory or gating, e.g. long short-term memory [LSTM] or gated recurrent units [GRU] - G06N 3/045: Combinations of networks - G06N 3/0464: Convolutional networks [CNN, ConvNet] - G06N 3/063: using electronic means - G06F 8/453: {Data distribution} - G06F 9/5055: {considering software capabilities, i.e. software resources associated or available to the machine} - G06F 2209/509: Offload - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - G06N: COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS ## Abstract Methods, apparatus, systems and articles of manufacture are disclosed to configure heterogenous components in an accelerator. An example apparatus includes a graph compiler to identify a workload node in a workload and generate a selector for the workload node, and the selector to identify an input condition and an output condition of a compute building block, wherein the graph compiler is to, in response to obtaining the identified input condition and output condition from the selector, map the workload node to the compute building block. ## Claims ### Claim 1 An apparatus comprising: a communication fabric; machine readable instructions; a secondary memory associated with a secondary programmable circuitry, the secondary programmable circuitry in communication with primary programmable circuitry, the primary programmable circuitry associated with a primary memory; the secondary programmable circuitry to at least one of instantiate or execute the machine readable instructions to: receive, via the communication fabric, a first workload from the primary programmable circuitry; allocate, via the communication fabric, a first memory portion to the first workload, the first memory portion located in either the primary memory or the secondary memory; receive, via the communication fabric, a second workload from the primary programmable circuitry; and allocate, via the communication fabric, a second memory portion to the second workload, the second memory portion located in either the primary memory or the secondary memory, the location of the second memory portion based on a relationship between the first workload and the second workload. ### Claim 2 (depends on 1) The apparatus of claim 1, wherein the location of the first memory portion is based on one or more allocation factors. ### Claim 3 (depends on 2) The apparatus of claim 2, wherein the one or more allocation factors include an amount of memory to be allocated, a type of the primary memory, a type of the secondary memory, an available capacity of the primary memory, and an available capacity of the secondary memory. ### Claim 4 (depends on 1) The apparatus of claim 1, wherein the secondary programmable circuitry is an Application Specific Integrated Circuit (ASIC). ### Claim 5 (depends on 1) The apparatus of claim 1, wherein the communication fabric includes peripheral component interconnect express (PCIE) circuitry to enable an exchange of data between the primary programmable circuitry and the secondary programmable circuitry. ### Claim 6 (depends on 1) The apparatus of claim 1, wherein the communication fabric implements an Advanced extensible Interface (AXI) protocol to enable an exchange of data between the secondary programmable circuitry and the secondary memory. ### Claim 7 (depends on 1) The apparatus of claim 1, wherein the machine readable instructions cause the secondary programmable circuitry to implement a plugin that allocates the first memory portion and the second memory portion. ### Claim 8 (depends on 7) The apparatus of claim 7, wherein: the primary programmable circuitry and the secondary programmable circuitry have heterogeneous hardware architectures; and the machine readable instructions cause the secondary programmable circuitry to provide a description of the heterogeneous hardware architectures to the plugin in a unified format. ### Claim 9 (depends on 1) The apparatus of claim 1, wherein the first workload corresponds to an artificial intelligence application. ### Claim 10 A secondary non-transitory machine readable storage medium comprising instructions associated with secondary programmable circuitry; the secondary programmable circuitry in communication with primary programmable circuitry, the primary programmable circuitry associated with a primary non-transitory machine readable storage medium, the instructions to cause the secondary programmable circuitry to at least: receive, via a communication fabric, a first workload from the primary programmable circuitry; allocate, via the communication fabric, a first memory portion to the first workload, the first memory portion located in either the primary non-transitory machine readable storage medium or the secondary non-transitory machine readable storage medium; receive, via the communication fabric, a second workload from the primary programmable circuitry; and allocate, via the communication fabric, a second memory portion to the second workload, the second memory portion located in either the primary non-transitory machine readable storage medium or the secondary non-transitory machine readable storage medium, the location of the second memory portion based on a relationship between the first workload and the second workload. ### Claim 11 (depends on 10) The secondary non-transitory machine readable storage medium of claim 10, wherein the location of the first memory portion is based on one or more allocation factors. ### Claim 12 (depends on 11) The secondary non-transitory machine readable storage medium of claim 11, wherein the one or more allocation factors include an amount of memory to be allocated, a type of the primary non-transitory machine readable storage medium, a type of the secondary non-transitory machine readable storage medium, an available capacity of the primary non-transitory machine readable storage medium, and an available capacity of the secondary non-transitory machine readable storage medium. ### Claim 13 (depends on 10) The secondary non-transitory machine readable storage medium of claim 10, wherein the secondary programmable circuitry is an Application Specific Integrated Circuit (ASIC). ### Claim 14 (depends on 10) The secondary non-transitory machine readable storage medium of claim 10, wherein the communication fabric includes peripheral component interconnect express (PCIE) circuitry to enable an exchange of data between the primary programmable circuitry and the secondary programmable circuitry. ### Claim 15 (depends on 10) The secondary non-transitory machine readable storage medium of claim 10, wherein the communication fabric implements an Advanced extensible Interface (AXI) protocol to enable an exchange of data between the secondary programmable circuitry and the secondary non-transitory machine readable storage medium. ### Claim 16 (depends on 10) The secondary non-transitory machine readable storage medium of claim 10, wherein the instructions cause the secondary programmable circuitry to implement a plugin that allocates the first memory portion and the second memory portion. ### Claim 17 (depends on 16) The secondary non-transitory machine readable storage medium of claim 16, wherein: the primary programmable circuitry and the secondary programmable circuitry have heterogeneous hardware architectures; and the instructions cause the secondary programmable circuitry to provide a description of the heterogeneous hardware architectures to the plugin in a unified format. ### Claim 18 (depends on 10) The secondary non-transitory machine readable storage medium of claim 10, wherein the first workload corresponds to an artificial intelligence application. ### Claim 19 A method comprising: executing instructions with secondary programmable circuitry associated with a second memory, the secondary programmable circuitry in communication with primary programmable circuitry, the primary programmable circuitry associated with a primary memory, wherein executing the instructions causes the secondary programmable circuitry to: receive, via a communication fabric, a first workload from the primary programmable circuitry; allocate, via the communication fabric, a first memory portion to the first workload, the first memory portion located in either the primary memory or the secondary memory; receive, via the communication fabric, a second workload from the primary programmable circuitry; and allocate, via the communication fabric, a second memory portion to the second workload, the second memory portion located in either the primary memory or the secondary memory, the location of the second memory portion based on a relationship between the first workload and the second workload. ### Claim 20 (depends on 19) The method of claim 19, wherein the location of the first memory portion is based on one or more allocation factors.