# US 12,217,061 B2 · Wavefront selection and execution > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,217,061 B2 - Document ID: US12217061B2 - Status: Granted - Kind: B2 - Application number: 18/309,536 - Filed: 2023-04-28 - Published: 2023-08-24 - Granted: 2025-02-04 - Earliest claimed: 2021-03-31 - Assignees: Advanced Micro Devices, Inc. - Applicants: Advanced Micro Devices, Inc. - Inventors: Maxim V. Kazakov - Web page: https://patentgrep.com/patent/US12217061B2 ## CPC - G06F 9/3885: {using a plurality of independent parallel functional units} - G06F 9/3012: {Organisation of register space, e.g. banked or distributed register file} - G06F 9/30152: {Determining start or end of instruction; determining instruction length} - G06F 9/3836: {Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution} - G06F 9/3851: {from multiple instruction streams, e.g. multistreaming} - G06F 9/3869: {Implementation aspects, e.g. pipeline latches; pipeline synchronisation and clocking} - G06F 9/3887: {controlled by a single instruction for multiple data lanes [SIMD]} - G06F 9/3889: {controlled by multiple instructions, e.g. MIMD, decoupled access or execute} - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract Techniques are provided for executing wavefronts. The techniques include at a first time for issuing instructions for execution, performing first identifying, including identifying that sufficient processing resources exist to execute a first set of instructions together within a processing lane; in response to the first identifying, executing the first set of instructions together; at a second time for issuing instructions for execution, performing second identifying, including identifying that no instructions are available for which sufficient processing resources exist for execution together within the processing lane; and in response to the second identifying, executing an instruction independently of any other instruction. ## Claims ### Claim 1 A method, comprising: at a first time for issuing instructions for execution, determining that, for a first set of instructions, bandwidth consumed by operands of the instructions of the first set of instructions is less than bandwidth available in register files, wherein the bandwidth available is based on operand slots; and in response to the determining, executing the first set of instructions together, wherein instructions that execute together access registers of a first slot together in a first clock cycle and access registers of a second slot together in a second clock cycle. ### Claim 2 (depends on 1) The method of claim 1, wherein the bandwidth comprises bandwidth available at ports of the register files. ### Claim 3 (depends on 2) The method of claim 2, wherein the ports comprise interfaces that allow functional units configured to execute instructions that access contents of registers of the register files. ### Claim 4 (depends on 1) The method of claim 1, wherein the bandwidth includes bandwidth for different types of register files. ### Claim 5 (depends on 4) The method of claim 4, wherein the different types of register files include a vector register file type and a scalar register file type. ### Claim 6 (depends on 4) The method of claim 4, wherein different types of register files have independently available bandwidth. ### Claim 7 (depends on 1) The method of claim 1, wherein the executing of the first set of instructions together is performed in response to also identifying that sufficient functional units exist within a processing lane to execute at least one operation of each instruction of the first set instructions in the same clock cycle. ### Claim 8 A compute unit, comprising: a memory configured to store instructions; and a processor, configured to: at a first time for issuing instructions for execution, determine that, for a first set of the instructions, bandwidth consumed by operands of the instructions of the first set of instructions is less than bandwidth available in register files, wherein the bandwidth available is based on operand slots; and in response to the determining, executing the first set of instructions together, wherein instructions that execute together access registers of a first slot together in a first clock cycle and access registers of a second slot together in a second clock cycle. ### Claim 9 (depends on 8) The compute unit of claim 8, wherein the bandwidth comprises bandwidth available at ports of the register files. ### Claim 10 (depends on 9) The compute unit of claim 9, wherein the ports comprise interfaces that allow functional units configured to execute instructions that access contents of registers of the register files. ### Claim 11 (depends on 8) The compute unit of claim 8, wherein the bandwidth includes bandwidth for different types of register files. ### Claim 12 (depends on 11) The compute unit of claim 11, wherein the different types of register files include a vector register file type and a scalar register file type. ### Claim 13 (depends on 11) The compute unit of claim 11, wherein different types of register files have independently available bandwidth. ### Claim 14 (depends on 8) The compute unit of claim 8, wherein the executing of the first set of instructions together is performed in response to also identifying that sufficient functional units exist within a processing lane to execute at least one operation of each instruction of the first set instructions in the same clock cycle. ### Claim 15 A non-transitory computer-readable medium storing instructions that, when executed by a processor, cause the processor to perform operations comprising: at a first time for issuing instructions for execution, determining that, for a first set of instructions, bandwidth consumed by operands of the instructions of the first set of instructions is less than bandwidth available in register files, wherein the bandwidth available is based on operand slots; and in response to the determining, executing the first set of instructions together, wherein instructions that execute together access registers of a first slot together in a first clock cycle and access registers of a second slot together in a second clock cycle. ### Claim 16 (depends on 15) The non-transitory computer-readable medium of claim 15, wherein the bandwidth comprises bandwidth available at ports of the register files. ### Claim 17 (depends on 16) The non-transitory computer-readable medium of claim 16, wherein the ports comprise interfaces that allow functional units configured to execute instructions that access contents of registers of the register files. ### Claim 18 (depends on 1) The method of claim 1, further comprising: at a second time for issuing instructions for execution, determining that there is no set of two or more available instructions for which bandwidth consumed by operands is less than the bandwidth available in the register files; and in response to the second determining, executing an available instruction independently of any other instruction. ### Claim 19 (depends on 8) The compute unit of claim 8, wherein the processor is further configured to: at a second time for issuing instructions for execution, second determining that the instructions do not include a set of two or more available instructions for which bandwidth consumed by operands is less than the bandwidth available in the register files; and in response to the second determining, executing an available instruction independently of any other instruction. ### Claim 20 (depends on 15) The non-transitory computer-readable medium of claim 15, wherein the operations further comprise: at a second time for issuing instructions for execution, second determining that there is no set of two or more available instructions for which bandwidth consumed by operands is less than the bandwidth available in the register files; and in response to the second determining, executing an available instruction independently of any other instruction.