# US 12,217,021 B2 · Processing unit with small footprint arithmetic logic unit > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,217,021 B2 - Document ID: US12217021B2 - Status: Granted - Kind: B2 - Application number: 18/219,268 - Filed: 2023-07-07 - Published: 2024-05-02 - Granted: 2025-02-04 - Earliest claimed: 2020-06-26 - Assignees: Advanced Micro Devices, Inc. - Applicants: Advanced Micro Devices, Inc. - Inventors: Bin He; Shubh Shah; Michael Mantor - Web page: https://patentgrep.com/patent/US12217021B2 ## CPC - G06F 7/57: Arithmetic logic units [ALU], i.e. arrangements or devices for performing two or more of the operations covered by groups G06F7/483 – G06F7/556 or for performing logical operations {(G06F7/49, G06F7/491 take precedence)} - G06F 5/012: {in floating-point computations} - G06F 7/483: Computations with numbers represented by a non-linear combination of denominational numbers, e.g. rational numbers, logarithmic number system or floating-point numbers {(G06F7/4806, G06F7/4824, G06F7/49, G06F7/491, G06F7/544 take precedence)} - G06F 7/5443: {Sum of products (for applications thereof, see the relevant places, e.g. G06F17/10, H03H17/00)} - G06F 17/16: Matrix or vector computation {, e.g. matrix-matrix or matrix-vector multiplication, matrix factorization (matrix transposition G06F7/78)} - G06N 3/063: using electronic means - G06N 3/08: Learning methods - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - G06N: COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS ## Abstract A parallel processing unit employs an arithmetic logic unit (ALU) having a relatively small footprint, thereby reducing the overall power consumption and circuit area of the processing unit. To support the smaller footprint, the ALU includes multiple stages to execute operations corresponding to a received instruction. The ALU executes at least one operation at a precision indicated by the received instruction, and then reduces the resulting data of the at least one operation to a smaller size before providing the results to another stage of the ALU to continue execution of the instruction. ## Claims ### Claim 1 A method comprising: executing a plurality of mathematical operations with a plurality of operands using an arithmetic logic unit (ALU); and reducing a first operand and a second operand of the plurality of operands by discarding at least a portion of each of the first operand and the second operand, wherein the discarded portion of the first operand and the discarded portion of the second operand include different numbers of bits. ### Claim 2 (depends on 1) The method of claim 1, wherein the mathematical operations are performed in response to a multiply-accumulate instruction. ### Claim 3 (depends on 2) The method of claim 2, wherein reducing the first operand comprises reducing the first operand at a sort-and-align stage of the ALU. ### Claim 4 (depends on 3) The method of claim 3, wherein the reducing the first operand comprises reducing the first operand by shifting a mantissa of the first operand to align with a mantissa of a second operand. ### Claim 5 (depends on 4) The method of claim 4, wherein shifting the mantissa of the first operand comprises shifting the mantissa of the first operand to align with the mantissa of the second operand in response to determining that the second operand is a largest operand of the plurality of operands. ### Claim 6 (depends on 4) The method of claim 4, further comprising: generating a sticky bit for the first operand based upon the discarded portion of the first operand. ### Claim 7 (depends on 4) The method of claim 4, further comprising: adding the shifted mantissa of the first operand to the second operand. ### Claim 8 A processing unit, comprising: an arithmetic logic unit (ALU) configured to execute a plurality of mathematical operations with a plurality of operands, wherein the ALU is further configured to reduce a first operand and a second operand of the plurality of operands by discarding at least a portion of each of the first operand and the second operand, and wherein the discarded portion of the first operand and the discarded portion of the second operand include different numbers of bits. ### Claim 9 (depends on 8) The processing unit of claim 8, wherein the mathematical operations are performed in response to a multiply-accumulate instruction. ### Claim 10 (depends on 9) The processing unit of claim 9, wherein the ALU includes a sort-and-align stage to reduce the first operand. ### Claim 11 (depends on 10) The processing unit of claim 10, wherein the sort-and-align stage is to reduce the first operand by shifting a mantissa of the first operand to align with a mantissa of a second operand. ### Claim 12 (depends on 11) The processing unit of claim 11, wherein the sort-and-align stage is to shift the mantissa of the first operand to align with the mantissa of the second operand in response to determining that the second operand is a largest operand of the plurality of operands. ### Claim 13 (depends on 11) The processing unit of claim 11 wherein the sort-and-align stage is to generate a sticky bit for the first operand based upon the discarded portion of the first operand. ### Claim 14 (depends on 11) The processing unit of claim 11, wherein the sort-and-align stage includes an adder to add the shifted mantissa of the first operand to the second operand. ### Claim 15 A non-transitory computer readable medium embodying a set of executable instructions, the set of executable instructions to manipulate at least one processor to: execute a plurality of mathematical operations with a plurality of operands using an arithmetic logic unit (ALU); and reduce a first operand and a second operand of the plurality of operands by discarding at least a portion of each of the first operand and the second operand, wherein the discarded portion of the first operand and the discarded portion of the second operand include different numbers of bits. ### Claim 16 (depends on 15) The computer readable medium of claim 15, wherein the mathematical operations are performed in response to a multiply-accumulate instruction. ### Claim 17 (depends on 16) The computer readable medium of claim 16, wherein reducing the first operand comprises reducing the first operand at a sort-and-align stage of the ALU. ### Claim 18 (depends on 17) The computer readable medium of claim 17, wherein the reducing the first operand comprises reducing the first operand by shifting a mantissa of the first operand to align with a mantissa of a second operand. ### Claim 19 (depends on 18) The computer readable medium of claim 18, wherein shifting the mantissa of the first operand comprises shifting the mantissa of the first operand to align with the mantissa of the second operand in response to determining that the second operand is a largest operand of the plurality of operands. ### Claim 20 (depends on 18) The computer readable medium of claim 18, wherein the instructions are further to manipulate the at least one processor to: generate a sticky bit for the first operand based upon the discarded portion of the first operand.