# US 12,216,978 B2 · Routing structure of semiconductor device and forming method thereof

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- Number: US 12,216,978 B2
- Document ID: US12216978B2
- Status: Granted
- Kind: B2
- Application number: 17/225,903
- Filed: 2021-04-08
- Published: 2022-10-13
- Granted: 2025-02-04
- Earliest claimed: 2021-04-08
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company Ltd.
- Inventors: Anurag Verma; Meng-Kai Hsu; Chih-Wei Chang; Sang-Chi Huang; Wei-Ling Chang; Hui-Zhong Zhuang
- Web page: https://patentgrep.com/patent/US12216978B2

## CPC

- G06F 30/3953: detailed
- H10W 20/43: Layouts of interconnections
- G06F 30/392: Floor-planning or layout, e.g. partitioning or placement
- G06F 30/394: Routing (G06F30/396 takes precedence)
- G06F 30/398: Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] (optical proximity correction [OPC] design processes G03F1/36)
- H10D 30/031: {of thin-film transistors [TFT]}
- H10D 30/6713: {characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes}
- H10D 30/6729: {characterised by the electrodes}
- H10D 30/6735: {having gates fully surrounding the channels, e.g. gate-all-around}
- H10D 62/118: {Nanostructure semiconductor bodies}
- H10D 64/01: Manufacture or treatment
- H10D 64/258: {characterised by the relative positions of the source or drain electrodes with respect to the gate electrode}
- H10D 84/83: of only insulated-gate FETs [IGFET]
- H10W 20/42: Vias, e.g. via plugs
- H10W 20/427: {Power or ground buses}
- G06F 2119/06: Power analysis or power optimisation
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A layout method and a semiconductor device are disclosed. The layout method includes: generating a design layout by placing a cell, wherein the cell includes: a first conductive segment overlapping a source/drain region and disposed immediately adjacent to a first power rail, wherein the first conductive segment has a length substantially equal to a cell length; a second conductive segment; and a third conductive segment between the first and second conductive segments. The layout method further includes: providing a fourth conductive segment and a fifth conductive segment to the design layout, wherein the fourth and fifth conductive segments are aligned in a first direction.

## Claims

### Claim 1

A layout method, executed by at least one processor, comprising:
determining a number M of tracks in a first direction for a cell, wherein M is a natural number;
generating a design layout by placing the cell, wherein the cell comprises:
a transistor disposed in a transistor layer having a gate electrode extending in the first direction;
a first power rail and a second power rail extending in a second direction perpendicular to the first direction in a first layer over the transistor layer, wherein the first power rail and the second power rail are disposed on opposite sides of the cell; and
a plurality of first conductive segments extending in the second direction between the first and second power rails in the first layer, wherein the first conductive segments are configured as input/output pins of the cell;
receiving a design rule check (DRC) deck, the DRC deck containing a minimal segment end spacing;
providing a third power rail extending in the first direction in a second layer over the first layer, the third power rail occupying one of the M tracks in the cell; and
in response to the occupied one of the M tracks, providing M second conductive segments extending in the first direction in the second layer, wherein each of the M second conductive segments is aligned with one of remaining M-1 tracks and configured to be electrically connected to one of the first conductive segments,
wherein at least two of the M second conductive segments are all aligned with a single track of the remaining M-1 tracks in the first direction and are separated by a spacing substantially equal to or greater than the minimal segment end spacing.

### Claim 2 (depends on 1)

The layout method according to claim 1,
wherein the third power rail extends throughout a height of the cell in the first direction in the second layer.

### Claim 3 (depends on 1)

The layout method according to claim 1, further comprising:
providing M-1 conductive vias electrically connecting the M-1 second conductive segments to the one of the first conductive segments,
wherein any two of the M-1 conductive vias are separated by a spacing substantially equal to or greater than a minimal via spacing contained in the DRC deck.

### Claim 4 (depends on 3)

The layout method according to claim 3, wherein at least two of the M-1 conductive vias are aligned in the first direction in one of the M tracks.

### Claim 5 (depends on 4)

The layout method according to claim 4, wherein, according to the DRC deck, a first distance between the at least two of the conductive vias is greater than a second distance between any other two of the conductive vias.

### Claim 6 (depends on 1)

The layout method according to claim 1, wherein the transistor further comprises a source/drain region, and at least one of the first conductive segments overlaps the source/drain region from a top-view perspective and is disposed immediately adjacent to the first power rail.

### Claim 7 (depends on 1)

The layout method according to claim 1, wherein one of the first conductive segments has a length greater than that of any other first conductive segment and is disposed immediately adjacent to the first power rail.

### Claim 8

A layout method, executed by at least one processor, the layout method comprising:
generating a design layout by placing a cell, wherein the cell comprises:
a first source/drain region and a second source/drain region in a first layer;
a gate electrode extending in a first direction in a second layer, wherein the cell further includes a plurality of tracks extending in the first direction;
a first power rail and a second power rail extending in a second direction perpendicular to the first direction in a third layer over the second layer, wherein the first power rail and the second power rail are on opposite sides of the cell; and
a plurality of conductive segments extending in the second direction between the first and second power rails in the third layer, wherein the plurality of conductive segments comprises:
a first conductive segment overlapping the first source/drain region from a top-view perspective and disposed immediately adjacent to the first power rail;
a second conductive segment overlapping the second source/drain region from a top-view perspective and disposed immediately adjacent to the second power rail;
a third conductive segment disposed between the first conductive segment and the second conductive segment; and
a third power rail extending in the first direction in a fourth layer over the third layer, the third power rail occupying one of the plurality of tracks in the cell; and
in response to the occupied one of the plurality of tracks, providing a fourth conductive segment and a fifth conductive segment to the design layout, wherein the fourth and fifth conductive segments extend in the first direction in the fourth layer and are both aligned with a single one of the plurality of tracks,
wherein a number of the plurality of conductive segments is equal to or greater than a number of the plurality of tracks.

### Claim 9 (depends on 8)

The layout method according to claim 8, further comprising:
providing a first conductive via to the design layout, wherein the first conductive via electrically connects the first conductive segment to the fourth conductive segment; and
providing a second conductive via to the design layout, wherein the second conductive via electrically connects the second conductive segment to the fifth conductive segment.

### Claim 10 (depends on 9)

The layout method according to claim 9, further comprising:
receiving a design rule check (DRC) deck, the DRC deck including a first distance, a second distance and a first length, wherein the first distance is a spacing between the first conductive via and the second conductive via, the second distance is a minimum spacing between the fourth conductive segment and the fifth conductive segment, and the first length is a minimum via enclosure length of the fourth conductive segment and the fifth conductive segment,
wherein the providing of the first conductive via and the providing of the second conductive via fulfills a requirement of the DRC that the first distance is greater than a sum of the second distance and twice the first length.

### Claim 11 (depends on 9)

The layout method according to claim 9, further comprising:
receiving a DRC deck, the DRC deck including a first distance and a second distance,
wherein the first distance is a spacing between the first conductive via and the second conductive via and the second distance is a spacing between the first conductive segment and the first power rail,
wherein the providing of the first conductive via and the providing of the second conductive via fulfills a requirement of the DRC that a ratio of the first distance to the second distance is greater than 5.5.

### Claim 12 (depends on 9)

The layout method according to claim 9, further comprising:
receiving a DRC deck, the DRC deck further including a first distance and a first width, wherein the first distance is a spacing between the first conductive via and the second conductive via and the first width is a width of each of the plurality of conductive segments measured in the first direction,
wherein the providing of the first conductive via and the providing of the second conductive via fulfills a requirement of the DRC that a value of the first width divided by the first distance is less than 0.24.

### Claim 13 (depends on 8)

The layout method according to claim 8, wherein the cell further comprises a third conductive via overlapping the first source/drain region from a top-view perspective and electrically connecting the first conductive segment to the gate electrode.

### Claim 14 (depends on 8)

The layout method according to claim 8, wherein a length of the first conductive segment is greater than or equal to a length of the third conductive segment.

### Claim 15 (depends on 14)

The layout method according to claim 14, wherein the first conductive segment has a length substantially equal to a cell length, measured in the second direction, of the cell.

### Claim 16 (depends on 8)

The layout method according to claim 8, wherein a length of the second conductive segment is substantially equal to or less than a length of the first conductive segment.

### Claim 17 (depends on 8)

The layout method according to claim 8, further comprising:
providing a sixth conductive segment to the design layout prior to the providing of the fourth conductive segment and the fifth conductive segment, wherein the sixth conductive segment extends in the first direction in the fourth layer.

### Claim 18

A layout method, executed by at least one processor, comprising:
determining a number M of tracks extending in a first direction for a cell, wherein M is a natural number;
receiving a design rule check (DRC) deck, the DRC deck including a minimal via spacing;
generating a design layout by placing the cell, wherein the cell comprises:
a transistor disposed in a transistor layer having a first source/drain region and a second source/drain region extending in a second direction, and a gate electrode extending in the first direction between the first source/drain region and the second source/drain region;
a first power rail and a second power rail extending in the second direction in a first layer over the transistor layer, wherein the first power rail and the second power rail are disposed on opposite sides of the cell; and
a plurality of first conductive segments extending in the second direction between the first and second power rails in the first layer;
providing a third power rail extending in the first direction in a second layer over the first layer, the third power rail occupying one of the M tracks in the cell;
in response to the occupied one of the M tracks, providing a number N of second conductive segments extending in the first direction in the second layer, N being a natural number greater than or equal to M, wherein each of the N second conductive segments corresponds to one of the M tracks and electrically connected to one of the first conductive segments, wherein two of the N second conductive segments are aligned to each other in the first direction and are both aligned with a single track of the M tracks; and
providing N conductive vias to electrically couple first conductive segments to the corresponding second conductive segments, wherein any two of the N conductive vias are separated by a spacing substantially at least equal to the minimal via spacing.

### Claim 19 (depends on 18)

The layout method according to claim 18, wherein a third segment of the first conductive segments has a length substantially equal to a cell length measured in the second direction.

### Claim 20 (depends on 18)

The layout method according to claim 18, wherein the two of the N conductive vias overlap an uppermost one and a lowest one, respectively, of the first conductive segments.