# US 12,216,976 B2 · Efficient integrated circuit simulation and testing

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- Number: US 12,216,976 B2
- Document ID: US12216976B2
- Status: Granted
- Kind: B2
- Application number: 17/485,168
- Filed: 2021-09-24
- Published: 2022-01-13
- Granted: 2025-02-04
- Earliest claimed: 2018-06-19
- Assignees: Proteantecs Ltd.
- Applicants: Proteantecs Ltd.
- Inventors: Evelyn Landman; Yair Talker; Eyal Fayneh; Yahel David; Shai Cohen; Inbar Weintrob
- Web page: https://patentgrep.com/patent/US12216976B2

## CPC

- G06F 30/3312: Timing analysis
- G06F 30/3315: using static timing analysis [STA]
- G06F 30/398: Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] (optical proximity correction [OPC] design processes G03F1/36)
- G06F 2111/08: Probabilistic or stochastic CAD
- G06F 2119/02: Reliability analysis or reliability optimisation; Failure analysis, e.g. worst case scenario performance, failure mode and effects analysis [FMEA]
- G06F 2119/04: Ageing analysis or optimisation against ageing
- G06F 2119/06: Power analysis or power optimisation
- G06F 2119/12: Timing analysis or timing optimisation
- G06F 2119/22: Yield analysis or yield optimisation
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

A method comprising using at least one hardware processor for: running a Monte Carlo simulation of possible integrated circuit (IC) process variations of each of a plurality of IC cell types, wherein each of the plurality of IC cell types is defined by multiple specific transistors and multiple specific interconnects; based on the results of the Monte Carlo simulation, creating a library of IC cell types and their corresponding behavioral values for each of the possible IC process variations, and storing the library in a non-transient memory; receiving an IC design embodied as a digital file; correlating the received IC design with the library; and predicting a frequency distribution and a power distribution of ICs manufactured according to the IC design.

## Claims

### Claim 1

A method comprising using at least one hardware processor for:
running a Monte Carlo simulation of possible integrated circuit (IC) process variations of each of a plurality of IC cell types;
based on results of the Monte Carlo simulation, creating a library of IC cell types and their corresponding behavioral values for each of the possible IC process variations;
receiving an IC design embodied as a digital file;
correlating the received IC design with the library; and
based on said correlating, predicting at least one of:
a frequency distribution, or
a power distribution,
of ICs manufactured according to the IC design.

### Claim 2 (depends on 1)

The method according to claim 1, wherein each of the plurality of IC cell types is defined by multiple specific transistors and multiple specific interconnects.

### Claim 3 (depends on 1)

The method according to claim 1, wherein said correlating comprises retrieving, from the library, behavioral values that pertain to cell types that exist in the IC design.

### Claim 4 (depends on 3)

The method according to claim 3, further comprising:
running an electronic circuit simulation of the IC design to identify possible IC process variations, based on the behavioral values retrieved from the library.

### Claim 5 (depends on 1)

The method according to claim 1, further comprising, based on said correlating:
predicting critical paths that limit a frequency of the ICs manufactured according to the IC design,
wherein said predicting of at least one of the frequency distribution and the power distribution is based on said critical paths prediction.

### Claim 6 (depends on 5)

The method according to claim 5, further comprising:
identifying a ranked list of the critical paths, out of paths in the IC design, based on the behavioral values retrieved from the library.

### Claim 7 (depends on 1)

The method according to claim 1, wherein the behavioral values are values that affect at least one operational parameter of an IC manufactured based on the IC design, wherein the at least one operational parameter is selected from the group consisting of: voltage, current, delay, and frequency.

### Claim 8 (depends on 1)

The method according to claim 1, wherein the library of IC cell types comprises an operational model for each IC cell type, the operational model comprising aging degradation data and a Static Timing Analysis (STA) model.

### Claim 9 (depends on 1)

The method according to claim 1, further comprising:
receiving Post-Si data, derived from ICs manufactured according to the IC design; and
adjusting the library based on the received Post-Si data.

### Claim 10 (depends on 9)

The method according to claim 9, further comprising:
receiving on-chip measurements from ICs manufactured according to the IC design, wherein the on-chip measurements are derived from one or more on-chip sensors of each of the manufactured ICs, wherein the one or more on-chip sensors comprise at least one of: a timing-margin sensor, a delay sensor, a leakage sensor, a voltage sensor, and a thermal sensor; and
using the on-chip measurements as an input to an estimator, the Post-Si data being provided as an output from the estimator.

### Claim 11 (depends on 1)

The method according to claim 1, further comprising:
(a) manufacturing ICs according to the IC design; and setting one or more operational parameters of the manufactured ICs based on the stored library; or
(b) setting one or more manufacturing parameters based on the stored library, and manufacturing ICs according to the IC design and the manufacturing parameters.

### Claim 12

A system comprising:
(a) at least one hardware processor; and
(b) a non-transitory computer-readable storage medium having program code embodied therewith, the program code executable by said at least one hardware processor to:
run a Monte Carlo simulation of possible integrated circuit (IC) process variations of each of a plurality of IC cell types,
based on results of the Monte Carlo simulation, create a library of IC cell types and their corresponding behavioral values for each of the possible IC process variations;
receive an IC design embodied as a digital file;
correlate the received IC design with the library, and
based on said correlating, predict at least one of:
a frequency distribution, or
a power distribution,
of ICs manufactured according to the IC design.

### Claim 13 (depends on 12)

The system according to claim 12, wherein each of the plurality of IC cell types is defined by multiple specific transistors and multiple specific interconnects.

### Claim 14 (depends on 12)

The system according to claim 12, wherein said correlating comprises retrieving, from the library, behavioral values that pertain to cell types that exist in the IC design.

### Claim 15 (depends on 14)

The system according to claim 14, wherein the program code is further executable to:
run an electronic circuit simulation of the IC design to identify possible IC process variations, based on the behavioral values retrieved from the library.

### Claim 16 (depends on 12)

The system according to claim 12, wherein the program code is further executable, based on said correlating, to:
predict critical paths that limit a frequency of the ICs manufactured according to the IC design,
wherein said predicting of at least one of the frequency distribution and the power distribution is based on said critical paths prediction.

### Claim 17 (depends on 16)

The system according to claim 16, wherein the program code is further executable to:
identify a ranked list of the critical paths, out of paths in the IC design, based on the behavioral values retrieved from the library.

### Claim 18 (depends on 12)

The system according to claim 12, wherein the behavioral values are values that affect at least one operational parameter of an IC manufactured based on the IC design, wherein the at least one operational parameter is selected from the group consisting of: voltage, current, delay, and frequency.

### Claim 19 (depends on 12)

The system according to claim 12, wherein the library of IC cell types comprises an operational model for each IC cell type, the operational model comprising aging degradation data and a Static Timing Analysis (STA) model.

### Claim 20 (depends on 12)

The system according to claim 12, wherein the program code is further executable to:
receive on-chip measurements from ICs manufactured according to the IC design, wherein the on-chip measurements are derived from one or more on-chip sensors of each of the manufactured ICs, wherein the one or more on-chip sensors comprise at least one of: a timing-margin sensor, a delay sensor, a leakage sensor, a voltage sensor, and a thermal sensor; and
operate an estimator to output Post-Si data based on the on-chip measurements; and
adjust the library based on the Post-Si data.