# US 12,216,940 B2 · UFS device for transmitting status information through AFC frame and operating method thereof

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- Number: US 12,216,940 B2
- Document ID: US12216940B2
- Status: Granted
- Kind: B2
- Application number: 18/351,498
- Filed: 2023-07-13
- Published: 2023-11-09
- Granted: 2025-02-04
- Earliest claimed: 2020-12-22
- Assignees: SK hynix Inc.
- Applicants: SK hynix Inc.
- Inventors: Moon Soo Choi
- Web page: https://patentgrep.com/patent/US12216940B2

## CPC

- G06F 3/0605: {by facilitating the interaction with a user or administrator}
- G06F 3/0659: {Command handling arrangements, e.g. command buffers, queues, command scheduling}
- G06F 3/0604: {Improving or facilitating administration, e.g. storage management}
- G06F 3/0653: {Monitoring storage devices or systems}
- G06F 3/0679: {Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]}
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

Embodiments of the present disclosure relate to an UFS device and an operating method thereof. According to the embodiments of the present disclosure, the UFS device may collect status information of the UFS device, create an Acknowledgement and Flow Control (AFC) frame including the collected status information, and transmit the AFC frame to a host performing communication with the UFS device.

## Claims

### Claim 1

A memory system comprising,
a memory device storing data; and
a memory controller configured to:
determine status information of the memory system,
generate a frame used for a flow control at a data link layer between a host and the memory system, and including a sequence number for data received by the memory system and the status information, and
transmit the frame to the host while the host is performing communication with the memory system through the data link layer,
wherein the memory controller is configured to generate the frame by:
writing the status information of the memory system to at least one status information register included in the memory system by executing an interrupt service routine for processing interrupt indicating a change of the status information, and
storing, in the frame, the status information of the memory written in the status information registers.

### Claim 2 (depends on 1)

The memory system of claim 1, wherein the status information includes at least one of temperature information of the memory system, voltage change information of the memory system, information on a communication layer between the host and the memory system, or command transmission hold request information for the host.

### Claim 3 (depends on 2)

The memory system of claim 2, wherein the communication layer is the data link layer or a physical layer.

### Claim 4 (depends on 2)

The memory system of claim 2, wherein the information on the communication layer includes at least one of error accumulation information which is information on errors accumulatively occurring in the communication layer, or error recovery information which is information on an operation of recovering the errors occurring in the communication layer.

### Claim 5 (depends on 1)

The memory system of claim 1, wherein the memory controller is configured to transmit the frame to the host at a link start-up time, a hibernate state exit time, or a data transfer time between the host and the memory system.

### Claim 6 (depends on 1)

The memory system of claim 1, wherein the memory system is a universal flash storage (UFS) device.

### Claim 7 (depends on 1)

The memory system of claim 1, wherein the frame is a Acknowledgement and Flow Control (AFC) frame.

### Claim 8 (depends on 1)

The memory system of claim 1, wherein the host and the memory system communicate each other according to a standard of Mobile Industry Processor Interface (MIPI).

### Claim 9 (depends on 1)

The memory system of claim 1, wherein the frame is used, when link startup operation or a hibernate state exit operation is executed, to check initial status of data link layer between the host and the memory system.

### Claim 10 (depends on 1)

The memory system of claim 1, wherein the memory controller is configured to monitor whether an interrupt, which indicates a change in a value of the status information, occurs.

### Claim 11 (depends on 1)

The memory system of claim 1, wherein the memory controller is configured to insert the status information into the frame used for the flow control between the host and the memory system on the data link.

### Claim 12 (depends on 1)

The memory system of claim 1, wherein the memory controller further includes a physical layer exchanging encoded symbols with the host.